Gap count analysis for the P1394a BUS

ABSTRACT

A method of optimizing communication over a high-speed serial bus by minimizing the delay between packets transmitted over the bus is disclosed. The method comprises: calculating the round trip delay between PHYs connected on the bus by pinging; a bus manager sending a configuration packet to all PHYs connected on the bus, the configuration packet containing a minimum gap_count parameter value; and all PHYs connected on the bus sending packets over the bus using the minimum gap_count parameter value as a delay between packets.

PRIORITY

This application is a continuation of co-owned U.S. patent application Ser. No. 10/749,791 of the same title, now issued as U.S. Pat. No. 7,308,517, filed Dec. 29, 2003, incorporated herein by reference in its entirety.

FIELD OF THE INVENTION

The present invention relates broadly to serial bus performance. Specifically, the present invention relates to improving bus performance by calculating the optimal gap_count parameter for a given topology utilizing a high-speed serial bus to connect devices.

BACKGROUND OF THE INVENTION

The Institute of Electrical and Electronic Engineers (IEEE) has promulgated a number of versions of a high-speed serial bus protocol falling under the IEEE 1394 family of standards (referred to herein collectively as “1394”). A typical serial bus having a 1394 architecture interconnects multiple node devices via point-to-point links, such as cables, each connecting a single node on the serial bus to another node on the serial bus. Data packets are propagated throughout the serial bus using a number of point-to-point transactions, such that a node that receives a packet from another node via a first point-to-point link retransmits the received packet via other point-to-point links. A tree network configuration and associated packet handling protocol ensures that each node receives every packet once. The 1394-compliant serial bus may be used as an alternate bus for the parallel backplane of a computer system, as a low cost peripheral bus, or as a bus bridge between architecturally compatible buses. Bus performance is gauged by throughput, or the amount of data that can be transmitted over the bus during a period of time.

There are several ways to improve bus performance. Devices connected to the bus can be arranged to minimize the longest round-trip delay between any two leaf nodes. This may involve either minimizing the number of cable connections between the farthest devices, reducing cable lengths, or both. Another way to improve bus performance is to group devices with identical speed capabilities next to one another. This avoids the creation of a “speed trap” when a slower device lies along the path between the two faster devices. Finally, bus performance can be improved by setting the PHY gap count parameter to the lowest workable value for a particular topology. However, determining this lowest workable value is problematic in that all of the variables affecting this value are unknown. Gap count parameters have been configured in the past using a subset of all possible variables, and the result is that the gap count is not optimal.

SUMMARY OF THE INVENTION

The present invention provides an optimal gap count that allows a high-speed serial bus to run faster and thus realize superior performance over prior buses. In an embodiment, bus management software sends a special PHY configuration packet that is recognized by all PHYs on the bus. The configuration packet contains a gap count value that all PHYs on the bus can use. As this gap count value decreases the time interval between packets that are transmitted, more real data can be transmitted over the bus per unit of time.

In an embodiment, the bus manager pings a PHY. The PHY sends a response to the ping, and a flight time value of the response from the PHY to the bus manager is added to calculate a round trip delay value. The ping command runs at the link layer level, from the link layer of one node to the link layer of another node. All flight time between link layer and PHY is ignored, and just the flight time from one PHY to another PHY is calculated. The ping time measured shows the link-to-link delay. The delay between the bus and the link is specified in the bus standard with minimum and maximum values. The PHY and link layer of a node is designed to be within that range specified by the standard. The round trip delay between nodes can be calculated as:

${{Round\_ Trip}{\_ Delay}_{\max}^{\lbrack{P_{X}{OP}_{Y}}\rbrack}} \leq {\begin{pmatrix} {{{Round\_ Trip}{\_ Delay}_{{Ping},\max}^{\lbrack{P_{BM}\mspace{11mu} O\mspace{11mu} P_{X}}\rbrack}} + {\underset{n}{\sum\limits^{({{BM},X})}}{2 \cdot {Jitter}_{n}}} +} \\ {{{Round\_ Trip}{\_ Delay}_{{Ping},\max}^{\lbrack{P_{BM}\; O\mspace{11mu} P_{Y}}\rbrack}} + {\underset{n}{\sum\limits^{({{BM},Y})}}{2 \cdot {Jitter}_{n}}} +} \\ {{PHY\_ DELAY}_{N,\max}^{P_{N}^{\prime}->P_{N}} + {{ARB\_ RESPONSE}{\_ DELAY}_{N,\max}^{P_{N}->P_{N}^{\prime}}}} \end{pmatrix} - \begin{pmatrix} {{{2 \cdot {Round\_ Trip}}{\_ Delay}_{{Ping},\min}^{\lbrack{P_{BM}{OP}_{N}}\rbrack}} + {4 \cdot {Jitter}_{N}} +} \\ {{PHY\_ DELAY}_{N,\min}^{P_{N}^{BM}->P_{N}^{\prime}} + {{ARB\_ RESPONSE}{\_ DELAY}_{N,\min}^{P_{N}^{\prime}->P_{N}^{BM}}} +} \\ {{PHY\_ DELAY}_{N,\min}^{P_{N}^{BM}->P_{N}} + {{ARB\_ RESPONSE}{\_ DELAY}_{N,\min}^{P_{N}->P_{N}^{BM}}}} \end{pmatrix}}$

This value can be communicated as the gap count parameter contained in the configuration packet, thus setting the gap between packets to an optimal value and increasing bus performance.

In another aspect of the invention, an apparatus for calculating and enforcing a substantially optimized gap count parameter is disclosed. In one embodiment, the apparatus comprises: a first module adapted to receive first data, the first data indicating the largest idle period allowable during a first interval; a second module adapted to receive second data, the second data indicating the largest period allowable for a second interval; and a third module adapted to calculate a gap parameter based at least in part upon the largest idle period allowable during the first interval, and the largest period allowable for the second interval.

In one variant, the first interval comprises a subaction.

In another variant, the first interval comprises an isochronous interval.

In yet another variant, the second interval comprises a subaction gap.

In still a further variant, the third module is further adapted to calculate a gap parameter by a process comprising setting a value such that the value exceeds the largest idle period allowable during the first interval. For example, the value may comprise a subaction gap timeout.

In still another variant, the third module is further adapted to calculate a gap parameter by a process comprising setting a value such that the value exceeds the largest period allowable for the second interval. For example, the value may comprise an arbitration reset gap.

In yet a further variant, the apparatus further comprises: a fourth module adapted to ensure that a first idle period observed is repeated with a period not less than the largest idle period allowable during the first interval; and a fifth module adapted to ensure that a second idle period observed is repeated with a period not less than the largest period allowable for the second interval.

In another aspect of the invention, a storage apparatus comprising a computer readable medium is disclosed. In one embodiment, the medium comprises a program having a plurality of instructions which, when executed by a computer, enforces a gap count parameter by: setting a first value to be greater than the largest idle period allowable during a first interval; setting a second value to be greater than the largest period allowable for a second interval; requiring that a first idle period observed is repeated with a period not less than the largest idle period allowable during the first interval; and requiring that a second idle period observed is repeated with a period not less than the largest period allowable for the second interval.

In one variant, the first interval comprises a subaction.

In another variant, the first interval comprises an isochronous interval.

In still another variant, the second interval comprises a subaction gap.

In yet another variant, the first value comprises a subaction gap timeout.

In a further variant, the second value comprises an arbitration reset timeout.

In yet another aspect of the invention, a method for enforcing a gap count parameter for use in a data bus is disclosed. In one embodiment, the method comprises: receiving first data, the first data indicating the largest idle period allowable during a first interval; receiving second data, the second data indicating the largest period allowable for a second interval; determining a gap count parameter based at least in part by setting a value greater than at least one of the first and second data.

In one variant, the first interval comprises at least one of a subaction and an isochronous interval.

In another variant, the second interval comprises a subaction gap.

In still another variant, the method further comprises requiring that a first idle period observed is repeated with a period not less than the largest idle period allowable during the first interval.

In yet another variant, the method further comprises requiring that a second idle period observed is repeated with a period not less than the largest period allowable for the second interval.

In a further aspect of the invention, an apparatus for enforcing a substantially optimized gap count parameter associated with a data bus is disclosed. In one embodiment, the apparatus comprises: a first module adapted to store a first variable greater than the largest idle period allowable during a first interval; a second module adapted to store a second variable greater than the largest period allowable for a second interval; a third module adapted to calculate a substantially optimal gap count parameter based at least in part upon the first and second variables; and a fourth module adapted to ensure that an idle period observed is not repeated with a period less than at least one of the first and second variables.

In one variant, the data bus comprises a serial bus, and the first interval comprises at least one of a subaction and an isochronous interval.

In another variant, the second interval comprises a subaction gap.

In yet another variant, the first variable comprises a subaction gap timeout value.

In still a further variant, the second variable comprises an arbitration reset timeout value.

In still another variant, the third module is further adapted to calculate a substantially optimal gap count parameter based at least in part upon a maximum round trip delay between a first PHY associated with a first node and a second PHY associated with a second node.

In still another aspect of the invention, a method for enforcing an optimized gap count parameter associated with a data bus is disclosed. In one embodiment, the method comprises: determining the largest idle period allowable during a first interval; determining the largest period allowable for a second interval; and deriving a gap count parameter based at least in part by setting a first value to be greater than the largest idle period allowable during the first interval, and based at least in part by setting a second value to be greater than the largest period allowable for the second interval.

In one variant, the method further comprises requiring that an idle period observed is not repeated with a period less than at least one of the largest idle period allowable during the first interval, and the largest period allowable for the second interval.

In another variant, the derivation of a gap count parameter is also based at least in part by calculating a maximum round trip delay between a first PHY associated with a first node and a second PHY associated with a second node.

Many other features and advantages of the present application will become apparent from the following detailed description considered in conjunction with the accompanying drawings, in which:

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates an intervening path model between two nodes, X & Y, and denotes the reference points required for a full analysis;

FIG. 2 illustrates ack/iso gap preservation, in the case where PHY X originated the most recent packet and PHY Y is responding (either with an ack or the next isochronous arbitration/packet).

FIG. 3 illustrates the sequence PHY Y will follow in responding to a received packet.

FIG. 4 illustrates subaction gap preservation, in the case where PHY X originated the most recent packet and PHY Y is responding after a subaction gap with arbitration for the current fairness interval.

FIG. 5 illustrates consistent subaction gap detection, in the case where PHY X originates an isochronous packet, observes a subaction_gap, and begins to drive an arbitration indication.

FIG. 6 illustrates an internal gap detection sequence, by showing the timing reference for relating the external gap detection times to the internal gap detection times.

FIG. 7 illustrates consistent arbitration reset gap detection, in the case where PHY X originates an asynchronous packet, observes an arbitration reset gap, and begins to drive an arbitration indication.

FIG. 8 illustrates a ping subaction issued by the link in Node X and directed to Node Y.

FIG. 9 illustrates a Bus Manager Leaf to Leaf topology.

FIG. 10 illustrates a topology where the bus manager is not a leaf but is part of the connecting path between the two leaves.

FIG. 11 illustrates a topology where the bus manager is not a leaf but is not part of the connecting path between the two leaves.

DETAILED DESCRIPTION

Four well known limiting corner cases for gap count are examined in an effort to find the minimum allowable gap count for a given topology. Both the table method and pinging method of determining the optimal gap count are explored.

It is important to note that this analysis assumes that PHY_DELAY can never exceed the maximum published in the PHY register set. However, corner conditions have been identified in which it is theoretically possible to have PHY_DELAY temporarily exceed the maximum published delay when repeating minimally spaced packets. Although not a rigorous proof, this phenomena is ignored for this analysis on the basis that it is presumed to be statistically insignificant.

The path between any two given PHYs can be represented as a daisy chain connection of the two devices with zero or more intervening, or repeating, PHYs. FIG. 1 illustrates such a path between two nodes, X & Y, and denotes the reference points required for a full analysis.

TABLE 1 Variable Definitions ARB_RESPONSE_DELAY_(n) ^(P) ^(n) ^(→P′) ^(n) Delay in propagating arbitration indication received from port P_(n) of PHY n to port P′_(n) of PHY n. BASERATE_(n) Fundamental operating frequency of PHY n. cable_delay_(n) One-way flight time of arbitration and data signals through cable_(n). The flight-time is assumed to be constant from one transmission to the next and symmetric. DATA_END_TIME_(n) ^(P) ^(n) Length of DATA_END transmitted on port P_(n) of PHY n. PHY_DELAY_(n) ^(P′) ^(n) ^(→P) ^(n) Time from receipt of first data bit at port P′_(n) of PHY n to re-transmission of same bit at port P_(n) of PHY n. RESPONSE_TIME_(n) ^(P′) ^(n) Idle time at port P′_(n) of PHY n between the reception of a inbound packet and the associated outbound arbitration indication for the subsequent packet intended to occur within the same isochronous interval or asynchronous subaction.

For any given topology, the gap count must be set such that an iso or ack gap observed/generated at one PHY isn't falsely interpreted as a subaction gap by another PHY in the network. Ack/Iso gaps are known to be at their largest nearest the PHY that originated the last packet. To ensure that the most recent originating PHY doesn't interrupt a subaction or isochronous interval with asynchronous arbitration, its subaction_gap timeout must be greater than the largest IDLE which can legally occur within a subaction or isochronous interval. FIG. 2 illustrates the case in which PHY X originated the most recent packet and PHY Y is responding (either with an ack or the next isochronous arbitration/packet).

For all topologies, the idle time observed at point Px must not exceed the subaction gap detection time: Idle_(max) ^(P) ^(X) <subaction_gap_(min) ^(P) ^(X)   (1)

The idle time at point Px can be determined by examining the sequence of time events in the network. All timing events are referenced to the external bus (as opposed to some internal point in the PHY).

-   -   t₀ First bit of packet sent at point P_(x)     -   t₁ Last bit of packet sent at point P_(x), DATA_END begins. t₁         follows t₀ by the length of the packet timed in PHY X's clock         domain.     -   t₂ DATA_END concludes at point P_(x), IDLE begins. t₂ follows t₁         by DATA_END_TIME_(X) ^(P) ^(X)     -   t₃ First bit of packet received at point P′_(Y). t₃ follows t₀         by all intervening cable_delay and PHY_DELAY instances.     -   t₄ Last bit of packet received at point P′_(Y). t₄ follows t₃ by         the length of the packet timed in PHY Y−1's clock domain.     -   t₅ DATA_END concludes at point P′_(Y), gap begins. t₅ follows t₄         by DATA_END_TIME_(Y−1) ^(P) ^(Y−1)     -   t₆ PHY Y responds with ack packet, isoch packet, or isoch         arbitration within RESPONSE_TIME_(Y) ^(P′) ^(Y) following t₅     -   t₇ Arbitration indication arrives at point P_(x). t₇ follows t₆         by the all intervening cable_delay and ARB_RESPONSE_DELAY         instances.

$\begin{matrix} {t_{1} = {t_{0} + \frac{packet\_ length}{{packet\_ speed} \cdot {BASERATE}_{X}}}} & (2) \\ {\begin{matrix} {t_{2} = {t_{1} + {{DATA\_ END}{\_ TIME}_{X}^{P_{X}}}}} \\ {= {t_{0} + \frac{packet\_ length}{{packet\_ speed} \cdot {BASERATE}_{X}} +}} \\ {{DATA\_ END}{\_ TIME}_{X}^{P_{X}}} \end{matrix}\begin{matrix} {t_{3} = {t_{0} + {cable\_ delay}_{X} + {\sum\limits_{n = {X + 1}}^{Y - 1}\left( {{cable\_ delay}_{n} + {PHY\_ DELAY}_{n}^{P_{n}^{\prime}->P_{n}}} \right)}}} & \; \end{matrix}} & \begin{matrix} (3) \\ \; \\ \; \\ \; \\ \; \\ (4) \end{matrix} \\ \begin{matrix} {t_{4} = {t_{3} + \frac{packet\_ length}{{packet\_ speed} \cdot {BASERATE}_{Y - 1}}}} \\ {= {t_{0} + {cable\_ delay}_{X} +}} \\ {{\sum\limits_{n = {X + 1}}^{Y - 1}\left( {{cable\_ delay}_{n} + {PHY\_ DELAY}_{n}^{P_{n}^{\prime}->P_{n}}} \right)} +} \\ {\frac{packet\_ length}{{packet\_ speed} \cdot {BASERATE}_{Y - 1}}} \end{matrix} & (5) \\ \begin{matrix} {t_{5} = {t_{4} + {{DATA\_ END}{\_ TIME}_{Y - 1}^{P_{Y - 1}}}}} \\ {= {t_{0} + {cable\_ delay}_{X} +}} \\ {{\sum\limits_{n = {X + 1}}^{Y - 1}\left( {{cable\_ delay}_{n} + {PHY\_ DELAY}_{n}^{P_{n}^{\prime}->P_{n}}} \right)} +} \\ {\frac{packet\_ length}{{packet\_ speed} \cdot {BASERATE}_{Y - 1}} + {{DATA\_ END}{\_ TIME}_{Y - 1}^{P_{Y - 1}}}} \end{matrix} & (6) \\ \begin{matrix} {t_{6} = {t_{5} + {RESPONSE\_ TIME}_{Y}^{P_{Y}^{\prime}}}} \\ {= {t_{0} + {cable\_ delay}_{X} +}} \\ {{\sum\limits_{n = {X + 1}}^{Y - 1}\left( {{cable\_ delay}_{n} + {PHY\_ DELAY}_{n}^{P_{n}^{\prime}->P_{n}}} \right)} +} \\ {\frac{packet\_ length}{{packet\_ speed} \cdot {BASERATE}_{Y - 1}} +} \\ {{{DATA\_ END}{\_ TIME}_{Y - 1}^{P_{Y - 1}}} + {RESPONSE\_ TIME}_{Y}^{P_{Y}^{\prime}}} \end{matrix} & (7) \\ \begin{matrix} {t_{7} = {t_{6} + {\sum\limits_{n = {X + 1}}^{Y - 1}\begin{pmatrix} {{cable\_ delay}_{n} +} \\ {{ARB\_ RESPONSE}{\_ DELAY}_{n}^{P_{n}->P_{n}^{\prime}}} \end{pmatrix}} +}} \\ {{cable\_ delay}_{X}} \\ {= {t_{0} + {\sum\limits_{n = {X + 1}}^{Y - 1}\begin{pmatrix} {{2 \cdot {cable\_ delay}_{n}} + {PHY\_ DELAY}_{n}^{P_{n}^{\prime}->P_{n}} +} \\ {{ARB\_ RESPONSE}{\_ DELAY}_{n}^{P_{n}->P_{n}^{\prime}}} \end{pmatrix}} +}} \\ {{2 \cdot {cable\_ delay}_{X}} + \frac{packet\_ length}{{packet\_ speed} \cdot {BASERATE}_{Y - 1}} +} \\ {{{DATA\_ END}{\_ TIME}_{Y - 1}^{P_{Y - 1}}} + {RESPONSE\_ TIME}_{Y}^{P_{Y}^{\prime}}} \end{matrix} & (8) \end{matrix}$ Given t₀ through t₇ above, the Idle time seen at point P_(x) is given as:

$\begin{matrix} \begin{matrix} {{Idle}^{P_{X}} = {t_{7} - t_{2}}} \\ {= {\sum\limits_{n = {X + 1}}^{Y - 1}\left( {{2 \cdot {cable\_ delay}_{n}} + {PHY\_ DELAY}_{n}^{P_{n}^{\prime}->P_{n}} +} \right.}} \\ {\left. {{ARB\_ RESPONSE}{\_ DELAY}_{n}^{P_{n}->P_{n}^{\prime}}} \right) +} \\ {{2 \cdot {cable\_ delay}_{X}} + {RESPONSE\_ TIME}_{Y}^{P_{Y}^{\prime}} +} \\ {{{DATA\_ END}{\_ TIME}_{Y - 1}^{P_{Y - 1}}} - {{DATA\_ END}{\_ TIME}_{X}^{P_{X}}} +} \\ {\frac{packet\_ length}{packet\_ speed} \cdot \left( {\frac{1}{{BASERATE}_{Y - 1}} - \frac{1}{{BASERATE}_{X}}} \right)} \end{matrix} & (9) \\ {{Let}\text{:}} & \; \\ {{DE\_ delta}^{\lbrack{P_{Y - 1},P_{X}}\rbrack} = {{{DATA\_ END}{\_ TIME}_{Y - 1}^{P_{Y - 1}}} - {{DATA\_ END}{\_ TIME}_{X}^{P_{X}}}}} & (10) \\ {{PPM\_ delta}^{\lbrack{{Y - 1},X}\rbrack} = {\frac{packet\_ length}{packet\_ speed} \cdot \left( {\frac{1}{{BASERATE}_{Y - 1}} - \frac{1}{{BASERATE}_{X}}} \right)}} & (11) \\ {{{{Round\_ Trip}{\_ Delay}^{\lbrack{P_{X}O\; P_{Y}}\rbrack}} = {{\sum\limits_{n = {X + 1}}^{Y - 1}\left( {{2 \cdot {cable\_ delay}_{n}} + {PHY\_ DELAY}_{n}^{P_{n}^{\prime}->P_{n}} + {{ARB\_ RESPONSE}{\_ DELAY}_{n}^{P_{n}->P_{n}^{\prime}}}} \right)} + {2 \cdot {cable\_ delay}_{X}}}}{{Then},}} & (12) \\ {{Idle}^{P_{X}} = {{{Round\_ Trip}{\_ Delay}^{\lbrack{P_{X}O\; P_{Y}}\rbrack}} + {RESPONSE\_ TIME}_{Y}^{P_{Y}^{\prime}} + {DE\_ delta}^{\lbrack{P_{Y - 1},P_{X}}\rbrack} + {PPM\_ delta}^{\lbrack{{Y - 1},X}\rbrack}}} & (13) \end{matrix}$ Substituting into Equation (1), Ack and Iso gaps are preserved network-wide if and only if:

$\begin{matrix} {\begin{bmatrix} {{{Round\_ Trip}{\_ Delay}^{\lbrack{P_{X}{OP}_{Y}}\rbrack}} +} \\ {{RESPONSE\_ TIME}_{Y}^{P_{Y}^{\prime}} +} \\ {{DE\_ delta}^{\lbrack{P_{Y - 1},P_{X}}\rbrack} +} \\ {PPM\_ delta}^{\lbrack{{Y - 1},X}\rbrack} \end{bmatrix}_{\max} < {subaction\_ gap}_{\min}^{P_{X}}} & (14) \end{matrix}$

The minimum subaction_gap at point Px isn't well known. IEEE1394-1995, in Table 4-33, defines the minimum subaction_gap timeout used at a PHY's internal state machines, not at the external interface. It has been argued that the internal and external representations of time may differ by as much as ARB_RESPONSE_DELAY when a PHY is counting elapsed time between an internally generated event and an externally received event. However, the ARB_RESPONSE_DELAY value for a particular PHY isn't generally known externally. Fortunately, the ARB_RESPONSE_DELAY value for a PHY whose FIFO is known to be empty is bounded by the worst case PHY_DELAY reported within the PHY register map. This suggests a realistic bound for the minimum subaction gap referenced at point Px:

$\begin{matrix} {{{subaction\_ gap}_{\min}^{P_{X}} \geq {{subaction\_ gap}_{\min}^{i_{X}} - {PHY\_ DELAY}_{X,\max}^{P_{X}}}}{where}} & (15) \\ {{subaction\_ gap}_{\min}^{i_{X}} = \frac{27 + {{gap\_ count} \cdot 16}}{{BASERATE}_{X,\max}}} & (16) \end{matrix}$ Combing Equations (14), (15), and (16):

$\begin{matrix} {\begin{bmatrix} {{{Round\_ Trip}{\_ Delay}^{\lbrack{P_{X}{OP}_{Y}}\rbrack}} +} \\ {{RESPONSE\_ TIME}_{Y}^{P_{Y}^{\prime}} +} \\ {{DE\_ delta}^{\lbrack{P_{Y - 1},P_{X}}\rbrack} +} \\ {PPM\_ delta}^{\lbrack{{Y - 1},X}\rbrack} \end{bmatrix}_{\max} < \left\lbrack \begin{matrix} {\frac{27 + {{gap\_ count} \cdot 16}}{{BASERATE}_{X,\max}} -} \\ {PHY\_ DELAY}_{X,\max}^{P_{X}} \end{matrix} \right\rbrack} & (17) \end{matrix}$ Solving for gap_count:

$\begin{matrix} {{gap\_ count} > \frac{{{BASERATE}_{X,\max} \cdot \left\lbrack \begin{matrix} {{{Round\_ Trip}{\_ Delay}_{\max}^{\lbrack{P_{X}{OP}_{Y}}\rbrack}} +} \\ {\begin{bmatrix} {{RESPONSE\_ TIME}_{Y}^{P_{Y}^{\prime}} +} \\ {{DE\_ delta}^{\lbrack{P_{Y - 1},P_{X}}\rbrack} +} \\ {PPM\_ delta}^{\lbrack{{Y - 1},X}\rbrack} \end{bmatrix}_{\max} +} \\ {PHY\_ DELAY}_{X,\max}^{P_{X}} \end{matrix} \right\rbrack} - 27}{(16)}} & (18) \end{matrix}$

Since RESPONSE_TIME, DE_delta, and PPM_delta are not independent parameters, the maximum of their sum is not accurately represented by the sum of their maximas. Finding a more accurate maximum for the combined quantity requires the identification of components of RESPONSE_TIME.

As specified in p1394a, RESPONSE_TIME includes the time a responding node takes to repeat the received packet and then drive a subsequent arbitration indication. (Note that by examination of the C code, RESPONSE_TIME is defined to include the time it takes to repeat a packet even if the PHY in question is a leaf node.) FIG. 3 illustrates the sequence PHY Y will follow in responding to a received packet. iy denotes the timings as seen/interpreted by the PHY state machine. Note that PY can be any repeating port on PHY Y. Consequently, the timing constraints referenced to PY in the following analysis must hold worst case for any and all repeating ports.

Beginning with the first arrival of data at P′Y (t3), the elaborated timing sequence for RESPONSE_TIME is:

-   -   t₃ First bit of packet received at point P′_(Y)     -   t₃′ First bit of packet repeated at point P_(Y). t₃′ lags t₃ by         PHY_DELAY     -   t₄ Last bit of packet received at point P′_(Y). t₄ follows t₃ by         the length of the packet timed in PHY N's clock domain. DATA_END         begins     -   t₄′ Last bit of packet repeated at point P_(Y). t₄′ lags t₃′ by         the length of the packet timed in PHY Y's clock domain. The PHY         begins “repeating” DATA_END     -   t₅ DATA_END concludes at point P′_(Y). t₅ follows t₄ by         DATA_END_TIME_(Y−1) ^(P) ^(Y−1)     -   t_(5a) stop_tx_packet( ) concludes at point i_(Y) and the state         machines command the PHY ports to stop repeating DATA_END.         t_(5a) leads t₅′ by any transceiver delay.     -   t₅′ DATA_END concludes at point P_(Y). t₅′ follows t₄′ by         DATA_END_TIME_(Y) ^(P) ^(Y)     -   t_(5b) start_tx_packet( ) commences at point i_(Y) and the state         machines command the PHY ports to begin driving the first         arbitration indication of any response. t_(5b) lags t_(5a) by an         IDLE_GAP and an unspecified state machine delay herein called         SM_DELAY.     -   t₆ PHY Y drives arbitration at points P′_(Y). t₆ follows t_(5b)         by any transceiver delay.

$\begin{matrix} {t_{3^{\prime}} = {t_{3} + {PHY\_ DELAY}_{Y}^{P_{Y}^{\prime}->P_{Y}}}} & (19) \\ \begin{matrix} {t_{4^{\prime}} = {t_{3^{\prime}} + \frac{packet\_ length}{{packet\_ speed} \cdot {BASERATE}_{Y}}}} \\ {= {t_{3} + {PHY\_ DELAY}_{Y}^{P_{Y}^{\prime}->P_{Y}} + \frac{packet\_ length}{{packet\_ speed} \cdot {BASERATE}_{Y}}}} \end{matrix} & (20) \\ \begin{matrix} {t_{5^{\prime}} = {t_{4^{\prime}} + {{DATA\_ END}{\_ TIME}_{Y}^{P_{Y}}}}} \\ {= {t_{3} + {PHY\_ DELAY}_{Y}^{P_{Y}^{\prime}->P_{Y}} +}} \\ {\frac{packet\_ length}{{packet\_ speed} \cdot {BASERATE}_{Y}} + {{DATA\_ END}{\_ TIME}_{Y}^{P_{Y}}}} \end{matrix} & (21) \\ \begin{matrix} {T_{5\; a} = {t_{5^{\prime}} - {transceiver\_ delay}_{Y}^{P_{Y}}}} \\ {= {t_{3} + {PHY\_ DELAY}_{Y}^{P_{Y}^{\prime}->P_{Y}} +}} \\ {\frac{packet\_ length}{{packet\_ speed} \cdot {BASERATE}_{Y}} +} \\ {{{DATA\_ END}{\_ TIME}_{Y}^{P_{Y}}} - {transceiver\_ delay}_{Y}^{P_{Y}}} \end{matrix} & (22) \\ \begin{matrix} {t_{5\; b} = {t_{5\; a} + {IDLE\_ GAP}_{Y} + {SM\_ DELAY}_{Y}}} \\ {= {t_{3} + {PHY\_ DELAY}_{Y}^{P_{Y}^{\prime}->P_{Y}} +}} \\ {\frac{packet\_ length}{{packet\_ speed} \cdot {BASERATE}_{Y}} + {{DATA\_ END}{\_ TIME}_{Y}^{P_{Y}}} +} \\ {{IDLE\_ GAP}_{Y} + {SM\_ DELAY}_{Y} - {transceiver\_ delay}_{Y}^{P_{Y}}} \end{matrix} & (23) \\ \begin{matrix} {t_{6} = {t_{5\; b} + {transceiver\_ delay}_{Y}^{P_{Y}^{\prime}}}} \\ {= {t_{3} + {PHY\_ DELAY}_{Y}^{P_{Y}^{\prime}->P_{Y}} +}} \\ {\frac{packet\_ length}{{packet\_ speed} \cdot {BASERATE}_{Y}} + {{DATA\_ END}{\_ TIME}_{Y}^{P_{Y}}} +} \\ {{IDLE\_ GAP}_{Y} + {SM\_ DELAY}_{Y} + {transceiver\_ delay}_{Y}^{P_{Y}^{\prime}} -} \\ {{transceiver\_ delay}_{Y}^{P_{Y}}} \end{matrix} & (24) \end{matrix}$ By definition, RESPONSE_TIME_(Y) ^(P′) ^(Y) =t ₆ −t ₅  (25) and through substitution:

$\begin{matrix} {{RESPONSE\_ TIME}_{Y}^{P_{Y}^{\prime}} = {{PHY\_ DELAY}_{Y}^{P_{Y}^{\prime}->P_{Y}} + {DE\_ delta}^{\lbrack{P_{Y},P_{Y - 1}}\rbrack} + {PPM\_ delta}^{\lbrack{Y,{Y - 1}}\rbrack} + {IDLE\_ GAP}_{Y} + {SM\_ DELAY}_{Y} + {transceiver\_ delay}_{Y}^{P_{Y}^{\prime}} - {transceiver\_ delay}_{Y}^{P_{Y}}}} & (26) \end{matrix}$ As such, the combination of RESPONSE_TIME, DE_delta, and PPM_delta from equation (18) can be represented as:

$\begin{matrix} {\left\lbrack \begin{matrix} {{RESPONSE\_ TIME}_{Y}^{P_{Y}^{\prime}} +} \\ {{DE\_ delta}^{\lbrack{P_{Y - 1},P_{X}}\rbrack} +} \\ {PPM\_ delta}^{\lbrack{{Y - 1},X}\rbrack} \end{matrix} \right\rbrack = {\begin{bmatrix} {{PHY\_ DELAY}_{Y}^{P_{Y}^{\prime}->P_{Y}} +} \\ {{DE\_ delta}^{\lbrack{P_{Y},P_{Y - 1}}\rbrack} +} \\ {{PPM\_ delta}^{\lbrack{Y,{Y - 1}}\rbrack} +} \\ {{IDLE\_ GAP}_{Y} + {SM\_ DELAY}_{Y} +} \\ {{transceiver\_ delay}_{Y}^{P_{Y}^{\prime}} -} \\ {{transceiver\_ delay}_{Y}^{P_{Y}} +} \\ {{DE\_ delta}^{\lbrack{P_{Y - 1},P_{X}}\rbrack} +} \\ {PPM\_ delta}^{\lbrack{{Y - 1},X}\rbrack} \end{bmatrix} = {\quad\left\lbrack \begin{matrix} {{PHY\_ DELAY}_{Y}^{P_{Y}^{\prime}->P_{Y}} + {DE\_ delta}^{\lbrack{P_{Y},P_{X}}\rbrack} +} \\ {{PPM\_ delta}^{\lbrack{Y,X}\rbrack} + {IDLE\_ GAP}_{Y} +} \\ {{SM\_ DELAY}_{Y} + {transceiver\_ delay}_{Y}^{P_{Y}^{\prime}} -} \\ {transceiver\_ delay}_{Y}^{P_{Y}} \end{matrix} \right\rbrack}}} & (27) \end{matrix}$ Noting that if PHYs X and Y−1 both adhere to the same minimum timing requirement for DATA_END_TIME and maximum timing requirement for BASE_RATE, then DE_delta_(max) ^([P) ^(Y) ^(,P) ^(X) ^(])=DE_delta_(max) ^([P) ^(Y) ^(,P) ^(Y−1) ^(]) PPM_delta_(max) ^([Y,X])=PPM_delta_(max) ^([Y,Y−1])  (28) The combined maximum can be rewritten as:

$\begin{matrix} {\begin{bmatrix} {{RESPONSE\_ TIME}_{Y}^{P_{Y}^{\prime}} +} \\ {{DE\_ delta}^{\lbrack{P_{Y - 1},P_{X}}\rbrack} +} \\ {PPM\_ delta}^{\lbrack{{Y - 1},X}\rbrack} \end{bmatrix}_{\max} = \begin{bmatrix} {{PHY\_ DELAY}_{Y,\max}^{P_{Y}^{\prime}->P_{Y}} +} \\ {{DE\_ delta}_{\max}^{\lbrack{P_{Y},P_{Y - 1}}\rbrack} +} \\ {{PPM\_ delta}_{\max}^{\lbrack{Y,{Y - 1}}\rbrack} +} \\ {{IDLE\_ GAP}_{Y,\max} +} \\ {{SM\_ DELAY}_{Y,\max} +} \\ {{transceiver\_ delay}_{Y,\max}^{P_{Y}^{\prime}} -} \\ {transceiver\_ delay}_{Y,\min}^{P_{Y}} \end{bmatrix}} & (29) \end{matrix}$ Comparing to equation (26) allows

$\begin{matrix} {\begin{bmatrix} {{RESPONSE\_ TIME}_{Y}^{P_{Y}^{\prime}} +} \\ {{DE\_ delta}^{\lbrack{P_{Y - 1},P_{X}}\rbrack} +} \\ {PPM\_ delta}^{\lbrack{{Y - 1},X}\rbrack} \end{bmatrix}_{\max} = {RESPONSE\_ TIME}_{Y,\max}^{P_{Y}^{\prime}}} & (30) \end{matrix}$ Finally:

$\begin{matrix} {{gap\_ count} > \frac{{{BASERATE}_{X,\max} \cdot \begin{bmatrix} {{{Round\_ Trip}{\_ Delay}_{\max}^{\lbrack{P_{X}O\mspace{11mu} P_{Y}}\rbrack}} +} \\ {{RESPONSE\_ TIME}_{Y,\max}^{P_{Y}^{\prime}} +} \\ {PHY\_ DELAY}_{X,\max}^{P_{X}} \end{bmatrix}} - 27}{16}} & (31) \end{matrix}$

For any given topology, the gap count must be set such that subaction gaps observed/generated at one PHY aren't falsely interpreted as arb_reset gaps by another PHY in the network. Subaction gaps are known to be at their largest nearest the PHY that originated the last packet. To ensure that the most recent originating PHY doesn't begin a new fairness interval before all PHYs exit the current one, its arb_reset_gap timeout must be greater than the largest subaction_gap which can legally occur. FIG. 4 illustrates the case in which PHY X originated the most recent packet and PHY Y is responding after a subaction gap with arbitration for the current fairness interval.

For all topologies, the idle time observed at point Px must not exceed the arbitration reset gap detection time: Idle_(max) ^(P) ^(X) <arb_reset_gap_(min) ^(P) ^(X)   (32)

The analysis is identical to the case in which Ack and Iso gaps are preserved with the exception that PHY Y takes longer to respond to the trailing edge of DATA_END. Let PHY Y have a response time of subaction_response_time. Then, Idle^(P) ^(X) =Round_Trip_Delay^([P) ^(X) ^(OP) ^(Y) ^(])+subaction_response_time_(Y) ^(P′) ^(Y) +DE_delta^([P) ^(Y−1) ^(,P) ^(X) ^(])+PPM_delta^([Y−1,X])  (33)

Substituting into Equation (32), subaction gaps are preserved network-wide if and only if:

$\begin{matrix} {\begin{bmatrix} {{{Round\_ Trip}{\_ Delay}^{\lbrack{P_{X}{OP}_{Y}}\rbrack}} +} \\ {{{subaction\_ response}{\_ time}_{Y}^{P_{Y}^{\prime}}} +} \\ {{DE\_ delta}^{\lbrack{P_{Y - 1},P_{X}}\rbrack} +} \\ {PPM\_ delta}^{\lbrack{{Y - 1},X}\rbrack} \end{bmatrix}_{\max} < {{arb\_ reset}{\_ gap}_{\min}^{P_{X}}}} & (34) \end{matrix}$

The minimum arb_reset_gap at point Px isn't well known. IEEE1394-1995, in Table 4-33, defines the minimum arb_reset_gap timeout used at a PHY's internal state machines, not at the external interface. It has been argued that the internal and external representations of time may differ by as much as ARB_RESPONSE_DELAY when a PHY is counting elapsed time between an internally generated event and an externally received event. However, the ARB_RESPONSE_DELAY value for a particular PHY isn't generally known externally. Fortunately, the ARB_RESPONSE_DELAY value for a PHY whose FIFO is known to be empty is bounded by the worst case PHY_DELAY reported within the PHY register map. This suggests a realistic bound for the minimum subaction gap referenced at point Px:

$\begin{matrix} {{{{arb\_ reset}{\_ gap}_{\min}^{P_{X}}} \geq {{{arb\_ reset}{\_ gap}_{\min}^{i_{X}}} - {PHY\_ DELAY}_{X,\max}^{P_{X}}}}{where}} & (35) \\ {{{arb\_ reset}{\_ gap}_{\min}^{i_{X}}} = \frac{51 + {{gap\_ count} \cdot 32}}{{BASERATE}_{X,\max}}} & (36) \end{matrix}$

The maximum subaction_response_time for PHY Y parallels the earlier dissection of RESPONSE_TIME. The timing sequence for subaction_response_time is identical to that of RESPONSE_TIME except that PHY Y, after concluding stop_tx_Packet( ), must wait to detect a subaction gap and then wait an additional arb_delay before calling start_tx_packet( ). Said differently, the idle period timed internally is a subaction gap plus arb_delay rather than an IDLE_GAP. Consequently, t5b becomes: t _(5b) =t _(5a)+subaction_gap^(i) ^(Y) +arb_delay^(i) ^(Y) +SM_DELAY_(Y)  (37) and subaction_response_time_(Y) ^(P′) ^(Y) =RESPONSE_TIME_(Y) ^(P′) ^(Y) −IDLE_GAP_(Y)+subaction_gap^(i) ^(Y) +arb_delay^(i) ^(Y)   (38) Substituting into Equation (34),

$\begin{matrix} {\begin{bmatrix} {{{Round\_ Trip}{\_ Delay}^{\lbrack{P_{X}{OP}_{Y}}\rbrack}} +} \\ {{RESPONSE\_ TIME}_{Y}^{P_{Y}^{\prime}} +} \\ {{DE\_ delta}^{\lbrack{P_{Y - 1},P_{X}}\rbrack} +} \\ {{PPM\_ delta}^{\lbrack{{Y - 1},X}\rbrack} +} \\ {{subaction\_ gap}^{i_{Y}} + {arb\_ delay}^{i_{Y}} -} \\ {IDLE\_ GAP}_{Y} \end{bmatrix}_{\max} < {{arb\_ reset}{\_ gap}_{\min}^{P_{X}}}} & (39) \end{matrix}$

Again, RESPONSE_TIME, DE_delta, and PPM_delta are not independent parameters. As shown previously, if PHYs X and Y−1 adhere to the same timing constant limits, the explicit DE_Delta and PPM_delta terms can be subsumed within RESPONSE_TIME giving:

$\begin{matrix} {{\begin{bmatrix} {{{Round\_ Trip}{\_ Delay}_{\max}^{p{\lbrack{P_{X}{OP}_{Y}}\rbrack}}} +} \\ {{RESPONSE\_ TIME}_{Y,\max}^{P_{Y}^{\prime}} +} \\ {{subaction\_ gap}_{\max}^{i_{Y}} + {arb\_ delay}_{\max}^{i_{Y}} -} \\ {{MIN\_ IDLE}{\_ TIME}_{Y}} \end{bmatrix} < {{arb\_ reset}{\_ gap}_{\min}^{P_{X}}}}{where}} & (40) \\ {{subaction\_ gap}_{\max}^{i_{Y}} = \frac{29 + {{gap\_ count} \cdot 16}}{{BASERATE}_{Y,\min}}} & (41) \\ {{{arb\_ delay}_{\max}^{i_{Y}} = \frac{{gap\_ count} \cdot 4}{{BASERATE}_{Y,\min}}}{and}} & (42) \\ {{IDLE\_ GAP}_{Y,\min} = {{MIN\_ IDLE}{\_ TIME}_{Y}}} & (43) \end{matrix}$ Combining Equations (35), (36), (40), (41), and (42):

$\begin{matrix} {\begin{bmatrix} {{{Round\_ Trip}{\_ Delay}_{\max}^{\lbrack{P_{X}{OP}_{Y}}\rbrack}} +} \\ {{RESPONSE\_ TIME}_{Y,\max}^{P_{Y}^{\prime}} -} \\ {{{MIN\_ IDLE}{\_ TIME}_{Y}} +} \\ \frac{29 + {{gap\_ count} \cdot 20}}{{BASERATE}_{Y,\min}} \end{bmatrix} < \left\lbrack \begin{matrix} {\frac{51 + {{gap\_ count} \cdot 32}}{{BASERATE}_{X,\max}} -} \\ {PHY\_ DELAY}_{X,\max}^{P_{X}} \end{matrix} \right\rbrack} & (44) \end{matrix}$ Solving for gap_count:

$\begin{matrix} {{gap\_ count} > \frac{\begin{matrix} {{{BASERATE}_{X,\max} \cdot \begin{bmatrix} {{{Round\_ Trip}{\_ Delay}_{\max}^{\lbrack{P_{X}{OP}_{Y}}\rbrack}} +} \\ {{RESPONSE\_ TIME}_{Y,\max}^{P_{Y}^{\prime}} -} \\ {{{MIN\_ IDLE}{\_ TIME}_{Y}} +} \\ {PHY\_ DELAY}_{X,\max}^{P_{X}} \end{bmatrix}} +} \\ {{29 \cdot \frac{{BASERATE}_{X,\max}}{{BASERATE}_{Y,\min}}} - 51} \end{matrix}}{32 - {20 \cdot \frac{{BASERATE}_{X,\max}}{{BASERATE}_{Y,\min}}}}} & (45) \end{matrix}$

For any given topology, the gap count must be set such that if a subaction gap is observed following an isochronous packet at one PHY, it is observed at all PHYs. The danger occurs when a subsequent arbitration indication is transmitted in the same direction as the previous data packet. Given that arbitration indications may propagate through intervening PHYs faster than data bits, gaps may be shortened as they are repeated. FIG. 5 illustrates the case in which PHY X originates an isochronous packet, observes a subaction_gap, and begins to drive an arbitration indication.

For all topologies, the minimum idle time observed at point P′Y must always exceed the maximum subaction gap detection time: Idle_(min) ^(P′) ^(Y) >subaction_gap_(max) ^(P′) ^(Y)   (46)

The time events t0 through t5 are identical to the previous analyses. In this scenario, t6 follows t2 by the time it takes PHY X to time subaction gap and arb_delay:

$\begin{matrix} \begin{matrix} {t_{6} = {t_{2} + {subaction\_ gap}^{P_{X}} + {arb\_ delay}}} \\ {= {t_{0} + \frac{packet\_ length}{{packet\_ speed} \cdot {BASERATE}_{X}} +}} \\ {{{DATA\_ END}{\_ TIME}_{X}^{P_{X}}} + {subaction\_ gap}^{P_{X}} +} \\ {{arb\_ delay}^{P_{X}}} \end{matrix} & (47) \end{matrix}$

The 1995 specification provides the timeouts used internally by the state machine. The externally observed timing requirements could differ (given possible mismatches in transceiver delay and state machines between the leading edge of IDLE and the leading edge of the subsequent arbitration indication). However, previous works have suggested any such delays could and should be well matched and that the external timing would follow the internal timing exactly.

Consequently, subaction_gap^(P) ^(X) +arb_delay^(P) ^(X) =subaction_gap^(i) ^(X) +arb_delay^(i) ^(X)   (48) T7 follows T6 by the time it takes the arbitration signal to propagate through the intervening PHYs and cables:

$\begin{matrix} \begin{matrix} {t_{7} = {t_{6} + {\sum\limits_{n = {X + 1}}^{Y - 1}\left( {{cable\_ delay}_{n} +} \right.}}} \\ {\left. {{ARB\_ RESPONSE}{\_ DELAY}_{n}^{P_{n}^{\prime}\rightarrow P_{n}}} \right) + {cable\_ delay}_{X}} \\ {= {t_{0} + \frac{packet\_ length}{{packet\_ speed} \cdot {BASERATE}_{X}} +}} \\ {{{DATA\_ END}{\_ TIME}_{X}^{P_{X}}} + {subaction\_ gap}^{i_{X}} +} \\ {{arb\_ delay}^{i_{X}} +} \\ {\sum\limits_{n = {X + 1}}^{Y - 1}\left( {{cable\_ delay}_{n} +} \right.} \\ {\left. {{ARB\_ RESPONSE}{\_ DELAY}_{n}^{P_{n}^{\prime}\rightarrow P_{n}}} \right) + {cable\_ delay}_{X}} \end{matrix} & (49) \end{matrix}$

Given t₀ through t₇ above, the Idle time seen at point P′_(Y) is given as:

$\begin{matrix} \begin{matrix} {{Idle}^{P_{Y}^{\prime}} = {t_{7} - t_{5}}} \\ {= {{subaction\_ gap}^{i_{X}} + {arb\_ delay}^{i_{X}} -}} \\ {\sum\limits_{n = {X + 1}}^{Y - 1}\left( {{PHY\_ DELAY}_{n}^{P_{n}^{\prime}\rightarrow P_{n}} -} \right.} \\ {\left. {{ARB\_ RESPONSE}{\_ DELAY}_{n}^{P_{n}^{\prime}\rightarrow P_{n}}} \right) -} \\ {{DE\_ delta}^{\lbrack{P_{Y - 1},P_{X}}\rbrack} - {PPM\_ delta}^{\lbrack{{Y - 1},X}\rbrack}} \end{matrix} & (50) \end{matrix}$ Let

$\begin{matrix} {{{Data\_ Arb}{\_ Mismatch}^{\lbrack{P_{X}\rightarrow P_{Y}}\rbrack}} = {\sum\limits_{n = {X + 1}}^{Y - 1}\left( {{PHY\_ DELAY}_{n}^{P_{n}^{\prime}\rightarrow P_{n}} - {{ARB\_ RESPONSE}{\_ DELAY}_{n}^{P_{n}^{\prime}\rightarrow P_{n}}}} \right)}} & (51) \end{matrix}$ Then,

$\begin{matrix} \begin{matrix} {{Idle}^{P_{Y}^{\prime}} = {t_{7} - t_{5}}} \\ {= {{subaction\_ gap}^{i_{X}} + {arb\_ delay}^{i_{X}} -}} \\ {{{Data\_ Arb}{\_ Mismatch}^{\lbrack{P_{X}\rightarrow P_{Y}}\rbrack}} - {DE\_ delta}^{\lbrack{P_{Y - 1},P_{X}}\rbrack} -} \\ {{PPM\_ delta}^{\lbrack{{Y - 1},X}\rbrack}} \end{matrix} & (52) \end{matrix}$

For the maximum subaction_gap detection time at point P′Y, the 1995 standard again only specifies the internal state machine timeout values. FIG. 6 provides the timing reference for relating the external gap detection times to the internal ones. The elaborated timing sequence is identical to the case for RESPONSE_TIME through point t5′. The remaining sequence is:

-   -   T₇ The arbitration indication launched by PHY X arrives at point         P′_(Y)     -   T_(7a) The arbitration indication launched by PHY X arrives at         point iY. t_(7a) lags t₇ by an unspecified arbitration detection         time, herein termed ARB_DETECTION_TIME         The externally seen gap at point P′_(Y) is given as         gap^(P′) ^(Y) =t ₇ −t ₅  (53)         The corresponding internal gap at point iY is         gap^(i) ^(Y) =t _(7a) −t _(5a)  (54)         Given that         t _(7a) =t ₇+ARB_DETECTION_TIME_(Y) ^(P′) ^(Y)   (55)         the external gap can be expressed as

$\begin{matrix} \begin{matrix} {{gap}^{P_{Y}^{\prime}} = {t_{7} - t_{5}}} \\ {= {t_{7a} - t_{5} - {{ARB\_ DETECTION}{\_ TIME}_{Y}^{P_{Y}^{\prime}}}}} \\ {= {t_{7a} - t_{5a} + t_{5a} - t_{5} - {{ARB\_ DETECTION}{\_ TIME}_{Y}^{P_{Y}^{\prime}}}}} \\ {= {{gap}^{i_{Y}} + t_{5a} - t_{5} - {{ARB\_ DECTECTION}{\_ TIME}_{Y}^{P_{Y}^{\prime}}}}} \\ {= {{gap}^{i_{Y}} + {PHY\_ DELAY}_{Y}^{P_{Y}^{\prime}\rightarrow P_{Y}} + {DE\_ delta}^{\lbrack{P_{Y},P_{Y - 1}}\rbrack} +}} \\ {{PPM\_ delta}^{\lbrack{Y,{Y - 1}}\rbrack} - {transceiver\_ delay}_{Y}^{P_{Y}} -} \\ {{ARB\_ DECTECTION}{\_ TIME}_{Y}^{P_{Y}^{\prime}}} \end{matrix} & (56) \end{matrix}$ Consequently,

$\begin{matrix} {{subaction\_ gap}^{P_{Y}^{\prime}} = {{subaction\_ gap}^{i_{Y}} + {PHY\_ DELAY}_{Y}^{P_{Y}^{\prime}\rightarrow P_{Y}} + {DE\_ delta}^{\lbrack{P_{Y},P_{Y - 1}}\rbrack} + {PPM\_ delta}^{\lbrack{Y,{Y - 1}}\rbrack} - {tranceiver\_ delay}_{Y}^{P_{Y}} - {{ARB\_ DECTECTION}{\_ TIME}_{Y}^{P_{Y}^{\prime}}}}} & (57) \end{matrix}$ Substituting (52) and (57) into (46) yields

$\begin{matrix} {\begin{bmatrix} {{subaction\_ gap}^{i_{X}} +} \\ {{arb\_ delay}^{i_{X}} -} \\ {{{Data\_ Arb}{\_ Mismatch}^{\lbrack{P_{X}\rightarrow P_{Y}}\rbrack}} -} \\ {{DE\_ delta}^{\lbrack{P_{Y - 1},P_{X}}\rbrack} -} \\ {PPM\_ delta}^{\lbrack{{Y - 1},X}\rbrack} \end{bmatrix} > \begin{bmatrix} {{subaction\_ gap}^{i_{Y}} +} \\ {{PHY\_ DELAY}_{Y}^{P_{Y}^{\prime}\rightarrow P} +} \\ {{DE\_ delta}^{\lbrack{P_{Y},P_{Y - 1}}\rbrack} +} \\ {{PPM\_ delta}^{\lbrack{Y,{Y - 1}}\rbrack} -} \\ {{transceiver\_ delay}_{Y}^{P_{Y}} -} \\ {{ARB\_ DETECTION}{\_ TIME}_{Y}^{P_{Y}^{\prime}}} \end{bmatrix}} & (58) \end{matrix}$ The inequality holds generally if

$\begin{matrix} {\begin{bmatrix} {{subaction\_ gap}^{i_{X}} +} \\ {arb\_ delay}^{i_{X}} \end{bmatrix}_{\min} > \begin{bmatrix} {{subaction\_ gap}^{i_{Y}} +} \\ {{PHY\_ DELAY}_{Y}^{P_{Y}^{\prime}\rightarrow P_{Y}} +} \\ {{DE\_ delta}^{\lbrack{P_{Y},P_{Y - 1}}\rbrack} +} \\ {{PPM\_ delta}^{\lbrack{Y,{Y - 1}}\rbrack} +} \\ {{DE\_ delta}^{\lbrack{P_{Y - 1},P_{X}}\rbrack} +} \\ {{PPM\_ delta}^{\lbrack{{Y - 1},X}\rbrack} +} \\ {{{Data\_ Arb}{\_ Mismatch}^{\lbrack{P_{X}\rightarrow P_{Y}}\rbrack}} -} \\ {{transceiver\_ delay}_{Y}^{P_{Y}} -} \\ {{ARB\_ DETECTION}{\_ TIME}_{Y}^{P_{Y}^{\prime}}} \end{bmatrix}_{\max}} & (59) \end{matrix}$ Combining the DE_Delta and PPM_delta terms gives:

$\begin{matrix} {\begin{bmatrix} {{subaction\_ gap}^{i_{X}} +} \\ {arb\_ delay}^{i_{X}} \end{bmatrix}_{\min} > \begin{bmatrix} {{subaction\_ gap}^{i_{Y}} +} \\ {{PHY\_ DELAY}_{Y}^{P_{Y}^{\prime}\rightarrow P_{Y}} +} \\ {{DE\_ delta}^{\lbrack{P_{Y},P_{X}}\rbrack} +} \\ {{PPM\_ delta}^{\lbrack{Y,X}\rbrack} +} \\ {{{Data\_ Arb}{\_ Mismatch}^{\lbrack{P_{X}\rightarrow P_{Y}}\rbrack}} -} \\ {{transceiver\_ delay}_{Y}^{P_{Y}^{\prime}} -} \\ {{ARB\_ DETECTION}{\_ TIME}_{Y}^{P_{Y}^{\prime}}} \end{bmatrix}_{\max}} & (60) \end{matrix}$ By assuming DE_delta^([P) ^(Y) ^(,P) ^(X) ^(])+PPM_delta^([Y,X])≦transceiver_delay_(Y) ^(P) ^(Y) +ARB_DETECTION_TIME_(Y) ^(P′) ^(Y)   (61) the constraining inequality can be further simplified to give

$\begin{matrix} {\begin{bmatrix} {{subaction\_ gap}_{\min}^{i_{X}} +} \\ {arb\_ delay}_{\min}^{i_{X}} \end{bmatrix} > \begin{bmatrix} {{subaction\_ gap}_{\max}^{i_{Y}} +} \\ {{PHY\_ DELAY}_{Y,\max}^{P_{Y}^{\prime}\rightarrow P_{Y}} +} \\ {{Data\_ Arb}{\_ Mismatch}_{\max}^{\lbrack{P_{X}\rightarrow P_{Y}}\rbrack}} \end{bmatrix}} & (62) \\ {{where}{{subaction\_ gap}_{\min}^{i_{X}} = \frac{27 + {{gap\_ count} \cdot 16}}{{BASERATE}_{X,\max}}}} & (63) \\ {{arb\_ delay}_{\min}^{i_{X}} = \frac{{gap\_ count} \cdot 4}{{BASERATE}_{X,\max}}} & (64) \\ {{and}{{subaction\_ gap}_{\max}^{i_{Y}} = \frac{29 + {{gap\_ count} \cdot 16}}{{BASERATE}_{Y,\min}}}} & (65) \end{matrix}$ Solving for gap count,

$\begin{matrix} {{gap\_ count} > \frac{\begin{matrix} {{{BASERATE}_{X,\max} \cdot \begin{bmatrix} {{PHY\_ DELAY}_{Y,\max}^{P_{Y}^{\prime}\rightarrow P_{Y}} +} \\ {{Data\_ Arb}{\_ Mismatch}_{\max}^{\lbrack{P_{X}\rightarrow P_{Y}}\rbrack}} \end{bmatrix}} +} \\ {{29 \cdot \frac{{BASERATE}_{X,\max}}{{BASERATE}_{Y,\min}}} - 27} \end{matrix}}{20 - {16 \cdot \frac{{BASERATE}_{X,\max}}{{BASERATE}_{Y,\min}}}}} & (66) \end{matrix}$

For any given topology, the gap count must be set such that if an arbitration reset gap is observed following an asynchronous packet at one PHY, it is observed at all PHYs. The danger occurs when a subsequent arbitration indication is transmitted in the same direction as the previous data packet. Given that arbitration indications may propagate through intervening PHYs faster than data bits, gaps may be shortened as they are repeated. FIG. 7 illustrates the case in which PHY X originates an asynchronous packet, observes an arbitration reset gap, and begins to drive an arbitration indication.

For all topologies, the minimum idle time observed at point P′Y must always exceed the maximum arbitration reset gap detection time: Idle_(min) ^(P′) ^(Y) >arb_reset_gap_(max) ^(P′) ^(Y)   (67)

The time events t0 through t5 are identical to the previous analyses. In this scenario, t6 follows t2 by the time it takes PHY X to time arb_reset_gap and arb_delay:

$\begin{matrix} \begin{matrix} {t_{6} = {t_{2} + {{arb\_ reset}{\_ gap}^{P_{X}}} + {arb\_ delay}^{P_{X}}}} \\ {= {t_{0} + \frac{packet\_ length}{{packet\_ speed} \cdot {BASERATE}_{X}} +}} \\ {{{DATA\_ END}{\_ TIME}_{X}^{P_{X}}} +} \\ {{{arb\_ reset}{\_ gap}^{P_{X}}} + {arb\_ delay}^{P_{X}}} \end{matrix} & (68) \end{matrix}$

The 1995 IEEE 1394 standard provides the timeouts used internally by the state machine. The externally observed timing requirements could differ (given possible mismatches in transceiver delay and state machines between the leading edge of IDLE and the leading edge of the subsequent arbitration indication). However, previous works have suggested any such delays could and should be well matched and that the external timing would follow the internal timing exactly. Consequently, arb_reset_gap^(P) ^(X) +arb_delay^(P) ^(X) =arb_reset_gap^(i) ^(X) +arb_delay^(i) ^(X)   (69)

T7 follows T6 by the time it takes the arbitration signal to propagate through the intervening PHYs and cables:

$\begin{matrix} \begin{matrix} {t_{7} = {t_{6} + {\sum\limits_{n = {X + 1}}^{Y - 1}\left( {{cable\_ delay}_{n} + {{ARB\_ RESPONSE}{\_ DELAY}_{n}^{P_{n}^{\prime}\rightarrow P_{n}}}} \right)} +}} \\ {{cable\_ delay}_{X}} \\ {= {t_{0} + \frac{packet\_ length}{{packet\_ speed} \cdot {BASERATE}_{X}} + {{DATA\_ END}{\_ TIME}_{X}^{P_{X}}} +}} \\ {{{arb\_ reset}{\_ gap}^{i_{X}}} + {arb\_ delay}^{i_{X}} +} \\ {{\sum\limits_{n = {X + 1}}^{Y - 1}\left( {{cable\_ delay}_{n} + {{ARB\_ RESPONSE}{\_ DELAY}_{n}^{P_{n}^{\prime}\rightarrow P_{n}}}} \right)} +} \\ {{cable\_ delay}_{X}} \end{matrix} & (70) \end{matrix}$

Given t0 through t7 above, the Idle time seen at point P′Y is given as:

$\begin{matrix} \begin{matrix} {{Idle}^{P_{Y}^{\prime}} = {t_{7} - t_{5}}} \\ {= {{{arb\_ reset}{\_ gap}^{i_{X}}} + {arb\_ delay}^{i_{X}} -}} \\ {{{Data\_ Arb}{\_ Mismatch}^{\lbrack{P_{X}\rightarrow P_{Y}}\rbrack}} - {DE\_ delta}^{\lbrack{P_{Y - 1},P_{X}}\rbrack} -} \\ {{PPM\_ delta}^{\lbrack{{Y - 1},X}\rbrack}} \end{matrix} & (71) \end{matrix}$

For the maximum arbitration_reset_gap detection time at point P′Y, equation (56) gives: arb_reset_gap^(P′) ^(Y) =arb_reset_gap^(i) ^(Y) +PHY_DELAY_(Y) ^(P′) ^(Y) ^(→P) ^(Y) +DE_delta^([P) ^(Y) ^(,P) ^(Y−1) ^(])+PPM_delta^([Y,Y−1])_transceiver_delay_(Y) ^(P) ^(Y) −ARB_DETECTION_TIME_(Y) ^(P′) ^(Y)   (72)

Substituting (71) and (72) into (67) yields

$\begin{matrix} {\begin{bmatrix} {{{arb\_ reset}{\_ gap}^{i_{X}}} +} \\ {{arb\_ delay}^{i_{X}} -} \\ {{{Data\_ Arb}{\_ Mismatch}^{\lbrack{P_{X}\rightarrow P_{Y}}\rbrack}} -} \\ {{DE\_ delta}^{\lbrack{P_{Y - 1},P_{X}}\rbrack} -} \\ {PPM\_ delta}^{\lbrack{{Y - 1},X}\rbrack} \end{bmatrix} > \mspace{230mu}\left\lbrack \begin{matrix} {{{arb\_ reset}{\_ gap}^{i_{Y}}} +} \\ {{PHY\_ DELAY}_{Y}^{P_{Y}^{\prime}\rightarrow P_{Y}} + {DE\_ delta}^{\lbrack{P_{Y},P_{Y - 1}}\rbrack} +} \\ {{PPM\_ delta}^{\lbrack{Y,{Y - 1}}\rbrack} - {transceiver\_ delay}_{Y}^{P_{Y}} -} \\ {{ARB\_ DETECTION}{\_ TIME}_{Y}^{P_{Y}^{\prime}}} \end{matrix} \right\rbrack} & (73) \end{matrix}$

The inequality holds generally if

$\begin{matrix} {\left\lbrack {{{arb\_ reset}{\_ gap}^{i_{X}}} + {arb\_ delay}^{i_{X}}} \right\rbrack_{\min} > \mspace{34mu}\begin{bmatrix} {{{arb\_ reset}{\_ gap}^{i_{Y}}} + {PHY\_ DELAY}_{Y}^{P_{Y}^{\prime}\rightarrow P_{Y}} +} \\ {{DE\_ delta}^{\lbrack{P_{Y},P_{Y - 1}}\rbrack} + {PPM\_ delta}^{\lbrack{Y,{Y - 1}}\rbrack} +} \\ {{DE\_ delta}^{\lbrack{P_{Y - 1},P_{X}}\rbrack} + {PPM\_ delta}^{\lbrack{{Y - 1},X}\rbrack} +} \\ {{{Data\_ Arb}{\_ Mismatch}^{\lbrack{P_{X}\rightarrow P_{Y}}\rbrack}} -} \\ {{transceiver\_ delay}_{Y}^{P_{Y}} - {{ARB\_ DETECTION}{\_ TIME}_{Y}^{P_{Y}^{\prime}}}} \end{bmatrix}_{\max}} & (74) \end{matrix}$

Combining the DE_Delta and PPM_delta terms gives:

$\begin{matrix} {\left\lbrack {{{arb\_ reset}{\_ gap}^{i_{X}}} + {arb\_ delay}^{i_{X}}} \right\rbrack_{\min} > \begin{bmatrix} {{{arb\_ reset}{\_ gap}^{i_{Y}}} + {PHY\_ DELAY}_{Y}^{P_{Y}^{\prime}\rightarrow P_{Y}} +} \\ {{DE\_ delta}^{\lbrack{P_{Y},P_{X}}\rbrack} + {PPM\_ delta}^{\lbrack{Y,X}\rbrack} +} \\ {{{Data\_ Arb}{\_ Mismatch}^{\lbrack{P_{X}\rightarrow P_{Y}}\rbrack}} -} \\ {{transceiver\_ delay}_{Y}^{P_{Y}} -} \\ {{ARB\_ DETECTION}{\_ TIME}_{Y}^{P_{Y}^{\prime}}} \end{bmatrix}_{\max}} & (75) \end{matrix}$

By requiring DE_delta^([P) ^(Y) ^(,P) ^(X) ^(])+PPM_delta^([Y,X])≦transceiver_delay_(Y) ^(P) ^(Y) +ARB_DETECTION_TIME_(Y) ^(P′) ^(Y) _(Y)  (76)

the constraining inequality can be further simplified to give

$\begin{matrix} {{\begin{bmatrix} {{{arb\_ reset}{\_ gap}_{\min}^{i_{X}}} +} \\ {arb\_ delay}_{\min}^{i_{X}} \end{bmatrix} > \begin{bmatrix} {{{arb\_ reset}{\_ gap}_{\max}^{i_{Y}}} +} \\ {{PHY\_ DELAY}_{Y,\max}^{P_{Y}^{\prime}\rightarrow P_{Y}} +} \\ {{Data\_ Arb}{\_ Mismatch}_{\max}^{\lbrack{P_{X}\rightarrow P_{Y}}\rbrack}} \end{bmatrix}}{where}} & (77) \\ {{{arb\_ reset}{\_ gap}_{\min}^{i_{X}}} = \frac{51 + {{gap\_ count} \cdot 32}}{{BASERATE}_{X,\max}}} & (78) \\ {{{arb\_ delay}_{\min}^{i_{X}} = \frac{{gap\_ count} \cdot 4}{{BASERATE}_{X,\max}}}{and}} & (79) \\ {{{arb\_ reset}{\_ gap}_{\max}^{i_{Y}}} = \frac{53 + {{gap\_ count} \cdot 32}}{{BASERATE}_{Y,\min}}} & (80) \end{matrix}$

Solving for gap count,

$\begin{matrix} {{gap\_ count} > \frac{\begin{matrix} {{{BASERATE}_{X,\max} \cdot \begin{bmatrix} {{PHY\_ DELAY}_{Y,\max}^{P_{Y}^{\prime}\rightarrow P_{Y}} +} \\ {{Data\_ Arb}{\_ Mismatch}_{\max}^{\lbrack{P_{X}\rightarrow P_{Y}}\rbrack}} \end{bmatrix}} +} \\ {{53 \cdot \frac{{BASERATE}_{X,\max}}{{BASERATE}_{Y,\min}}} - 51} \end{matrix}}{36 - {32 \cdot \frac{{BASERATE}_{X,\max}}{{BASERATE}_{Y,\min}}}}} & (81) \end{matrix}$

Equations (31), (45), (66) and (81) place a lower bound on gap count. Let:

$\begin{matrix} {{gap\_ count}_{A} = \frac{\begin{matrix} {{BASERATE}_{X,\max} \cdot} \\ {\begin{bmatrix} {{{Round\_ Trip}{\_ Delay}_{\max}^{\lbrack{P_{X}O\mspace{11mu} P_{Y}}\rbrack}} +} \\ {{RESPONSE\_ TIME}_{Y,\max}^{P_{Y}^{\prime}} +} \\ {PHY\_ DELAY}_{X,\max}^{P_{X}} \end{bmatrix} - 27} \end{matrix}}{16}} & (82) \\ {{gap\_ count}_{B} = \frac{\begin{matrix} {{{BASERATE}_{X,\max} \cdot \begin{bmatrix} {{{Round\_ Trip}{\_ Delay}_{\max}^{\lbrack{P_{X}O\mspace{11mu} P_{Y}}\rbrack}} +} \\ {{RESPONSE\_ TIME}_{Y,\max}^{P_{Y}^{\prime}} -} \\ {{{MIN\_ IDLE}{\_ TIME}_{Y}} +} \\ {PHY\_ DELAY}_{X,\max}^{P_{X}} \end{bmatrix}} +} \\ {{29 \cdot \frac{{BASERATE}_{X,\max}}{{BASERATE}_{Y,\min}}} - 51} \end{matrix}}{32 - {20 \cdot \frac{{BASERATE}_{X,\max}}{{BASERATE}_{Y,\min}}}}} & (83) \\ {{gap\_ count}_{C} = \frac{\begin{matrix} {{{BASERATE}_{X,\max} \cdot \begin{bmatrix} {{{Data\_ Arb}{\_ Mismatch}_{\max}^{\lbrack{P_{X}\rightarrow P_{Y}}\rbrack}} +} \\ {PHY\_ DELAY}_{Y,\max}^{P_{Y}^{\prime}\rightarrow P_{Y}} \end{bmatrix}} +} \\ {{29 \cdot \frac{{BASERATE}_{X,\max}}{{BASERATE}_{Y,\min}}} - 27} \end{matrix}}{20 - {16 \cdot \frac{{BASERATE}_{X,\max}}{{BASERATE}_{Y,\min}}}}} & (84) \\ {{gap\_ count}_{D} = \frac{\begin{matrix} {{{BASERATE}_{X,\max} \cdot \begin{bmatrix} {{{Data\_ Arb}{\_ Mismatch}_{\max}^{\lbrack{P_{X}\rightarrow P_{Y}}\rbrack}} +} \\ {PHY\_ DELAY}_{Y,\max}^{P_{Y}^{\prime}\rightarrow P_{Y}} \end{bmatrix}} +} \\ {{53 \cdot \frac{{BASERATE}_{X,\max}}{{BASERATE}_{Y,\min}}} - 51} \end{matrix}}{36 - {32 \cdot \frac{{BASERATE}_{X,\max}}{{BASERATE}_{Y,\min}}}}} & (85) \end{matrix}$

Given the ratio of maximum to minimum BASERATE is always >1 and that MIN_IDLE_TIME is ˜40 ns, it is clear that: gap_count_(B)>gap_count_(A)  (86) and gap_count_(D)>gap_count_(C)  (87)

To select an appropriate gap count for a given topology, both gap countB and gap_countD must be calculated, rounded up to the next integer, and the maximum of the two results selected.

For IEEE1394-1995 style topologies (assumed to be limited to 4.5 m cables and a worst case PHY_DELAY of 144 ns), a table can be constructed to provide the gap count setting as a function of hops. In constructing such a table, the constant values in Table 2 are assumed.

TABLE 2 PHY Timing Constants Parameter Minimum Maximum ARB_RESPONSE_DELAY¹ PHY_DELAY(max) − 60 ns PHY_DELAY(max) BASERATE 98.294 mbps 98.314 mbps cable_delay 22.725 ns MIN_IDLE_TIME 40 ns PHY_DELAY 144 ns RESPONSE_TIME PHY_DELAY + 100 ns

The resulting gap count versus Cable Hops can then be calculated:

TABLE 3 Gap Count as a function of hops Hops Gap Count 1 5 2 7 3 8 4 10 5 13 6 16 7 18 8 21 9 24 10 26 11 29 12 32 13 35 14 37 15 40 16 43 17 46 18 48 19 51 20 54 21 57 22 59 23 62

Pinging provides an effective way to set an optimal gap count for topologies with initially unspecified or unknown PHY or cable delays. Specifically, pinging allows determination of an instantaneous Round_Trip_Delay between two given points. Once the worst case Round_Trip Delay has been determined via pinging, gap_countb and gap_countd can be calculated and the appropriate gap count selected.

The Jitter value specified in the PHY register map was introduced to help relate instantaneous measurements of ROUND_TRIP_DELAY to the maximum possible ROUND_TRIP_DELAY between two points. Specifically, the outbound PHY_DELAY and return ARB_RESPONSE_DELAY measured between a given ordered pair of ports on a PHY (say P_(c) out to and back from P_(d)) can be related to the maximum outbound PHY_DELAY and return ARB_RESPONSE_DELAY between any and all ordered pairs of ports (referenced as P_(a) & P_(b)) on the same PHY:

$\begin{matrix} {0 \leq \begin{bmatrix} {\frac{\begin{matrix} {{PHY\_ DELAY}_{n,\max}^{P_{a}\rightarrow P_{b}} +} \\ {{ARB\_ RESPONSE}{\_ DELAY}_{n,\max}^{P_{b}\rightarrow P_{a}}} \end{matrix}}{2} -} \\ \frac{\begin{matrix} {{PHY\_ DELAY}_{n,{meas}}^{P_{c}\rightarrow P_{d}} +} \\ {{ARB\_ RESPONSE}{\_ DELAY}_{n,{meas}}^{P_{d}\rightarrow P_{c}}} \end{matrix}}{2} \end{bmatrix} \leq {Jitter}_{n}} & (88) \end{matrix}$

Noting that a measured value can never exceed a maximum value between order ports, the following corollary relating two independent measurements can be proven for any and all combination of ordered ports:

$\begin{matrix} {\begin{bmatrix} {\frac{\begin{matrix} {{PHY\_ DELAY}_{n,{meas}_{1}}^{P_{a}\rightarrow P_{b}} +} \\ {{ARB\_ RESPONSE}{\_ DELAY}_{n,{meas}_{1}}^{P_{b}\rightarrow P_{a}}} \end{matrix}}{2} -} \\ \frac{\begin{matrix} {{PHY\_ DELAY}_{n,{meas}_{2}}^{P_{c}\rightarrow P_{d}} +} \\ {{ARB\_ RESPONSE}{\_ DELAY}_{n,{meas}_{2}}^{P_{d}\rightarrow P_{c}}} \end{matrix}}{2} \end{bmatrix} \leq {Jitter}_{n}} & (89) \end{matrix}$

In order for a bus manager to calculate ordered leaf-to-leaf delays via a series of ping requests launched from the bus manager, a number of ROUND_TRIP_DELAY relationships will be required and are derived below. Round_Trip_Delay_(max) ^([P) ^(X) ^(OP) ^(Y) ^(])

Using the definition of Round_Trip_Delay first provided in equation (12) as guidance, the roundtrip delay between Nodes X and Y from the perspective of Node X can be written as:

$\begin{matrix} {{{Round\_ Trip}{\_ Delay}_{\max}^{\lbrack{P_{X}\mspace{11mu} O\mspace{11mu} P_{Y}}\rbrack}} = {{\sum\limits_{n = {X + 1}}^{Y - 1}\begin{pmatrix} {{2 \cdot {cable\_ delay}_{n}} +} \\ {{PHY\_ DELAY}_{n,\max}^{P_{n}^{\prime}\rightarrow P_{n}} +} \\ {{ARB\_ RESPONSE}{\_ DELAY}_{n,\max}^{P_{n}\rightarrow P_{n}^{\prime}}} \end{pmatrix}} + {2 \cdot {cable\_ delay}_{X}}}} & (90) \end{matrix}$

From equation (88), the maximum PHY_DELAY and ARB_RESPONSE_DELAY between an ordered pair of ports can be bounded by the measured delays plus the overall jitter sum yielding:

$\begin{matrix} {{{Round\_ Trip}{\_ Delay}_{\max}^{\lbrack{P_{X}\mspace{11mu} O\mspace{11mu} P_{Y}}\rbrack}} \leq {{\sum\limits_{n = {X + 1}}^{Y - 1}\begin{pmatrix} {{2 \cdot {cable\_ delay}_{n}} +} \\ {{PHY\_ DELAY}_{n,{meas}_{1}}^{P_{n}^{\prime}\rightarrow P_{n}} +} \\ {{{ARB\_ RESPONSE}{\_ DELAY}_{n,{meas}_{1}}^{P_{n}\rightarrow P_{n}^{\prime}}} +} \\ {2 \cdot {Jitter}_{n}} \end{pmatrix}} + {2 \cdot {cable\_ delay}_{X}}}} & (91) \end{matrix}$

Comparison to the definition of Round_Trip_Delay then allows

$\begin{matrix} {{{{Round\_ Trip}{\_ Delay}_{\max}^{\lbrack{P_{X}\mspace{11mu} O\mspace{11mu} P_{Y}}\rbrack}} \leq {{{Round\_ Trip}{\_ Delay}_{{meas}_{1}}^{\lbrack{P_{X}\mspace{11mu} O\mspace{11mu} P_{Y}}\rbrack}} + {\sum\limits_{n = {X + 1}}^{Y - 1}{2 \cdot {Jitter}_{n}}}}}\mspace{20mu}{{Round\_ Trip}{\_ Delay}_{\max}^{\lbrack{P_{Y}\mspace{11mu} O\mspace{11mu} P_{X}}\rbrack}}} & (92) \end{matrix}$

Using the definitions of Round_Trip_Delay first provided in equation (12) as guidance, the roundtrip delay between Nodes X and Y from the perspective of Node Y can be written as:

$\begin{matrix} {{{Round\_ Trip}{\_ Delay}_{\max}^{\lbrack{P_{Y}\mspace{11mu} O\mspace{11mu} P_{X}}\rbrack}} = {{\sum\limits_{n = {X + 1}}^{Y - 1}\begin{pmatrix} {{2 \cdot {cable\_ delay}_{n}} +} \\ {{PHY\_ DELAY}_{n,\max}^{P_{n}\rightarrow P_{n}^{\prime}} +} \\ {{ARB\_ RESPONSE}{\_ DELAY}_{n,\max}^{P_{n}^{\prime}\rightarrow P_{n}}} \end{pmatrix}} + {2 \cdot {cable\_ delay}_{X}}}} & (93) \end{matrix}$

From equation (88), the maximum PHY_DELAY and ARB_RESPONSE_DELAY between an ordered pair of ports can be related to the measured delays observed in the reverse direction:

$\begin{matrix} {\begin{pmatrix} {{PHY\_ DELAY}_{n,\max}^{P_{n}\rightarrow P_{n}^{\prime}} +} \\ {{ARB\_ RESPONSE}{\_ DELAY}_{n,\max}^{P_{n}^{\prime}\rightarrow P_{n}}} \end{pmatrix} \leq {{2 \cdot {Jitter}_{n}} + \begin{pmatrix} {{PHY\_ DELAY}_{n,{meas}_{1}}^{P_{n}^{\prime}\rightarrow P_{n}} +} \\ {{ARB\_ RESPONSE}{\_ DELAY}_{n,{meas}_{1}}^{P_{n}\rightarrow P_{n}^{\prime}}} \end{pmatrix}}} & (94) \end{matrix}$

allowing the maximum round trip between Nodes X and Y to be rewritten as:

$\begin{matrix} {{{{Round\_ Trip}{\_ Delay}_{\max}^{\lbrack{P_{Y}{OP}_{X}}\rbrack}} \leq {{\sum\limits_{n = {X + 1}}^{Y - 1}\begin{pmatrix} {{2 \cdot {cable\_ delay}_{n}} +} \\ {{PHY\_ DELAY}_{n,{meas}}^{P_{n}^{\prime}->P_{n}} +} \\ {{{ARB\_ RESPONSE}{\_ DELAY}_{n,{meas}}^{P_{n}->P_{n}^{\prime}}} +} \\ {2 \cdot {Jitter}_{n}} \end{pmatrix}} + {2 \cdot {cable\_ delay}_{X}}}}\;} & (95) \end{matrix}$

Comparison to the definition of Round_Trip_Delay then allows

$\begin{matrix} {{{Round\_ Trip}{\_ Delay}_{\max}^{\lbrack{P_{Y}{OP}_{X}}\rbrack}} \leq {{{Round\_ Trip}{\_ Delay}_{{meas}_{1}}^{\lbrack{P_{X}{OP}_{Y}}\rbrack}} + {\sum\limits_{n = {X + 1}}^{Y - 1}{2 \cdot {Jitter}_{n}}}}} & (96) \\ {{Round\_ Trip}{\_ Delay}_{\max}^{\lbrack{P_{N}{OP}_{X}}\rbrack}} & \; \end{matrix}$

Using the definition of Round_Trip_Delay first provided in equation (12) as guidance, the roundtrip delay between Nodes N and Y from the perspective of Node N can be written as:

$\begin{matrix} {{{Round\_ Trip}{\_ Delay}_{\max}^{\lbrack{P_{N}{OP}_{Y}}\rbrack}} = {{\sum\limits_{n = {N + 1}}^{Y - 1}\begin{pmatrix} {{2 \cdot {cable\_ delay}_{n}} +} \\ {{PHY\_ DELAY}_{n,\max_{1}}^{P_{n}^{\prime}->P_{n}} +} \\ {{ARB\_ RESPONSE}{\_ DELAY}_{n,\max}^{P_{n}->P_{n}^{\prime}}} \end{pmatrix}} + {2 \cdot {cable\_ delay}_{N}}}} & (97) \end{matrix}$

From equation (88), the maximum PHY_DELAY and ARB_RESPONSE_DELAY between an ordered pair of ports can be bounded by the measured delays plus the overall jitter sum yielding:

$\begin{matrix} {{{Round\_ Trip}{\_ Delay}_{\max}^{\lbrack{P_{N}{OP}_{Y}}\rbrack}} \leq {{\sum\limits_{n = {N + 1}}^{Y - 1}\begin{pmatrix} {{2 \cdot {cable\_ delay}_{n}} +} \\ {{PHY\_ DELAY}_{n,{meas}_{1}}^{P_{n}^{\prime}->P_{n}} +} \\ {{{ARB\_ RESPONSE}{\_ DELAY}_{n,{meas}_{1}}^{P_{n}->P_{n}^{\prime}}} +} \\ {2 \cdot {Jitter}_{n}} \end{pmatrix}} + {2 \cdot {cable\_ delay}_{N}}}} & (98) \end{matrix}$

Introducing offsetting terms to the right side:

$\begin{matrix} \begin{matrix} {{{Round\_ Trip}{\_ Delay}_{\max}^{\lbrack{P_{N}{OP}_{Y}}\rbrack}} \leq {{\sum\limits_{n = {X + 1}}^{Y - 1}\begin{pmatrix} {{2 \cdot {cable\_ delay}_{n}} + {PHY\_ DELAY}_{n,{meas}_{1}}^{P_{n}^{\prime}->P_{n}} +} \\ {{{ARB\_ RESPONSE}{\_ DELAY}_{n,{meas}_{1}}^{P_{n}->P_{n}^{\prime}}} +} \\ {2 \cdot {Jitter}_{n}} \end{pmatrix}} +}} \\ {{2 \cdot {cable\_ delay}_{X}} -} \\ {{\sum\limits_{n = {X + 1}}^{N - 1}\begin{pmatrix} {{2 \cdot {cable\_ delay}_{n}} + {PHY\_ DELAY}_{n,{meas}_{1}}^{P_{n}^{\prime}->P_{n}} +} \\ {{{ARB\_ RESPONSE}{\_ DELAY}_{n,{meas}_{1}}^{P_{n}->P_{n}^{\prime}}} +} \\ {2 \cdot {Jitter}_{n}} \end{pmatrix}} -} \\ {{2 \cdot {cable\_ delay}_{X}} - {PHY\_ Delay}_{N,{meas}_{1}}^{P_{N}^{\prime}->P_{N}} -} \\ {{{ARB\_ RESPONSE}{\_ DELAY}_{N,{meas}_{1}}^{P_{N}->P_{N}^{\prime}}} - {2 \cdot {Jitter}_{N}}} \end{matrix} & (99) \end{matrix}$

Equations (89) and the fact that measured delays are at no smaller than minimum delays allow simplification to:

$\begin{matrix} \begin{matrix} {{{Round\_ Trip}{\_ Delay}_{\max}^{\lbrack{P_{N}{OP}_{Y}}\rbrack}} \leq {{\sum\limits_{n = {X + 1}}^{Y - 1}\begin{pmatrix} {{2 \cdot {cable\_ delay}_{n}} + {PHY\_ DELAY}_{n,{meas}_{1}}^{P_{n}^{\prime}->P_{n}} +} \\ {{{ARB\_ RESPONSE}{\_ DELAY}_{n,{meas}_{1}}^{P_{n}->P_{n}^{\prime}}} +} \\ {2 \cdot {Jitter}_{n}} \end{pmatrix}} +}} \\ {{2 \cdot {cable\_ delay}_{X}} -} \\ {{\sum\limits_{n = {X + 1}}^{N - 1}\begin{pmatrix} {{2 \cdot {cable\_ delay}_{n}} + {PHY\_ DELAY}_{n,{meas}_{2}}^{P_{n}^{\prime}->P_{n}} +} \\ {{ARB\_ RESPONSE}{\_ DELAY}_{n,{meas}_{2}}^{P_{n}->P_{n}^{\prime}}} \end{pmatrix}} -} \\ {{2 \cdot {cable\_ delay}_{X}} - {PHY\_ Delay}_{N,\min}^{P_{N}^{\prime}->P_{N}} -} \\ {{{ARB\_ RESPONSE}{\_ DELAY}_{N,\min}^{P_{N}->P_{N}^{\prime}}} - {2 \cdot {Jitter}_{N}}} \end{matrix} & (100) \end{matrix}$

Comparison to the definition of Round_Trip_Delay then allows

$\begin{matrix} \begin{matrix} {{{Round\_ Trip}{\_ Delay}_{\max}^{\lbrack{P_{N}{OP}_{Y}}\rbrack}} \leq {{{Round\_ Trip}{\_ Delay}_{{meas}_{1}}^{\lbrack{P_{X}{OP}_{Y}}\rbrack}} +}} \\ {{\sum\limits_{n = {X + 1}}^{Y - 1}{2 \cdot {Jitter}_{n}}} -} \\ {{{Round\_ Trip}{\_ Delay}_{{meas}_{2}}^{\lbrack{P_{X}{OP}_{N}}\rbrack}} -} \\ {{PHY\_ DELAY}_{N,\min}^{P_{N}^{\prime}->P_{N}} -} \\ {{{ARB\_ RESPONSE}{\_ DELAY}_{N,\min}^{P_{N}->P_{N}^{\prime}}} -} \\ {2 \cdot {Jitter}_{N}} \\ {{Round\_ Trip}{\_ Delay}_{\max}^{\lbrack{P_{Y}{OP}_{N}}\rbrack}} \end{matrix} & (101) \end{matrix}$

Using the definition of Round_Trip_Delay first provided in equation (12) as guidance, the roundtrip delay between Nodes N and Y from the perspective of Node Y can be written as:

$\begin{matrix} {{{Round\_ Trip}{\_ Delay}_{\max}^{\lbrack{P_{Y}{OP}_{N}}\rbrack}} = {{\sum\limits_{n = {N + 1}}^{Y - 1}\begin{pmatrix} {{2 \cdot {cable\_ delay}_{n}} + {PHY\_ DELAY}_{n,\max}^{P_{n}->P_{n}^{\prime}} +} \\ {{ARB\_ RESPONSE}{\_ DELAY}_{n,\max}^{P_{n}^{\prime}->P_{n}}} \end{pmatrix}} + {2 \cdot {cable\_ delay}_{N}}}} & (102) \end{matrix}$

From equation (88), the maximum PHY_DELAY and ARB_RESPONSE_DELAY between an ordered pair of ports can be related to the measured delays observed in the reverse direction:

$\begin{matrix} {\begin{pmatrix} {{PHY\_ DELAY}_{n,\max}^{P_{n}->P_{n}^{\prime}} +} \\ {{ARB\_ RESPONSE}{\_ DELAY}_{n,\max}^{P_{n}^{\prime}->P_{n}}} \end{pmatrix} \leq {{2 \cdot {Jitter}_{n}} + \begin{pmatrix} {{PHY\_ DELAY}_{n,{meas}_{1}}^{P_{n}^{\prime}->P_{n}} +} \\ {{ARB\_ RESPONSE}{\_ DELAY}_{n,{meas}_{1}}^{P_{n}->P_{n}^{\prime}}} \end{pmatrix}}} & (103) \end{matrix}$

allowing the maximum round trip between Nodes N and Y to be rewritten as:

$\begin{matrix} {{{Round\_ Trip}{\_ Delay}_{\max}^{\lbrack{P_{Y}{OP}_{N}}\rbrack}} \leq {{\sum\limits_{n = {N + 1}}^{Y - 1}\begin{pmatrix} {{2 \cdot {cable\_ delay}_{n}} +} \\ {{PHY\_ DELAY}_{n,{meas}_{1}}^{P_{n}^{\prime}->P_{n}} +} \\ {{{ARB\_ RESPONSE}{\_ DELAY}_{n,{meas}_{1}}^{P_{n}->P_{n}^{\prime}}} +} \\ {2 \cdot {Jitter}_{n}} \end{pmatrix}} + {2 \cdot {cable\_ delay}_{N}}}} & (104) \end{matrix}$

Introducing offsetting terms to the right side:

$\begin{matrix} {{{Round\_ Trip}{\_ Delay}_{\max}^{\lbrack{P_{Y}{OP}_{N}}\rbrack}} \leq {{\sum\limits_{n = {X + 1}}^{Y - 1}\begin{pmatrix} {{2 \cdot {cable\_ delay}_{n}} + {PHY\_ DELAY}_{n,{meas}_{1}}^{P_{n}^{\prime}->P_{n}} +} \\ {{{ARB\_ RESPONSE}{\_ DELAY}_{n,{meas}_{1}}^{P_{n}->P_{n}^{\prime}}} +} \\ {2 \cdot {Jitter}_{n}} \end{pmatrix}} +}} \\ {{2 \cdot {cable\_ delay}_{X}} -} \\ {{\sum\limits_{n = {X + 1}}^{N - 1}\begin{pmatrix} {{2 \cdot {cable\_ delay}_{n}} + {PHY\_ DELAY}_{n,{meas}_{1}}^{P_{n}^{\prime}->P_{n}} +} \\ {{{ARB\_ RESPONSE}{\_ DELAY}_{n,{meas}_{1}}^{P_{n}->P_{n}^{\prime}}} +} \\ {2 \cdot {Jitter}_{n}} \end{pmatrix}} -} \\ {{2 \cdot {cable\_ delay}_{X}} - {PHY\_ Delay}_{N,{meas}_{1}}^{P_{N}^{\prime}->P_{N}} -} \\ {{{ARB\_ RESPONSE}{\_ DELAY}_{N,{meas}_{1}}^{P_{N}->P_{N}^{\prime}}} - {2 \cdot {Jitter}_{N}}} \end{matrix}$

Equations (89) and the fact that measured delays are at no smaller than minimum delays allow simplification to:

$\begin{matrix} \begin{matrix} {{{Round\_ Trip}{\_ Delay}_{\max}^{\lbrack{P_{Y}{OP}_{N}}\rbrack}} \leq {{\sum\limits_{n = {X + 1}}^{Y - 1}\begin{pmatrix} {{2 \cdot {cable\_ delay}_{n}} + {PHY\_ DELAY}_{n,{meas}_{1}}^{P_{n}^{\prime}->P_{n}} +} \\ {{{ARB\_ RESPONSE}{\_ DELAY}_{n,{meas}_{1}}^{P_{n}->P_{n}^{\prime}}} +} \\ {2 \cdot {Jitter}_{n}} \end{pmatrix}} +}} \\ {{2 \cdot {cable\_ delay}_{X}} -} \\ {{\sum\limits_{n = {X + 1}}^{N - 1}\begin{pmatrix} {{2 \cdot {cable\_ delay}_{n}} + {PHY\_ DELAY}_{n,{meas}_{2}}^{P_{n}^{\prime}->P_{n}} +} \\ {{ARB\_ RESPONSE}{\_ DELAY}_{n,{meas}_{2}}^{P_{n}->P_{n}^{\prime}}} \end{pmatrix}} -} \\ {{2 \cdot {cable\_ delay}_{X}} - {PHY\_ Delay}_{N,\min}^{P_{N}^{\prime}->P_{N}} -} \\ {{{ARB\_ RESPONSE}{\_ DELAY}_{N,\min}^{P_{N}->P_{N}^{\prime}}} - {2 \cdot {Jitter}_{N}}} \end{matrix} & (105) \end{matrix}$

Comparison to the definition of Round_Trip_Delay then allows

$\begin{matrix} \begin{matrix} {{{Round\_ Trip}{\_ Delay}_{\max}^{\lbrack{P_{Y}{OP}_{N}}\rbrack}} \leq {{{Round\_ Trip}{\_ Delay}_{{meas}_{1}}^{\lbrack{P_{X}{OP}_{Y}}\rbrack}} +}} \\ {{\sum\limits_{n = {X + 1}}^{Y - 1}{2 \cdot {Jitter}_{n}}} -} \\ {{{Round\_ Trip}{\_ Delay}_{{meas}_{2}}^{\lbrack{P_{X}{OP}_{N}}\rbrack}} -} \\ {{PHY\_ DELAY}_{N,\min}^{P_{N}^{\prime}->P_{N}} -} \\ {{{ARB\_ RESPONSE}{\_ DELAY}_{N,\min}^{P_{N}->P_{N}^{\prime}}} -} \\ {2 \cdot {Jitter}_{N}} \end{matrix} & (107) \end{matrix}$

PHY pinging provides a low level mechanism to directly measure round trip delays between two nodes by timing link initiated subactions. However, pinging does introduce some uncertainty in the measured delay. Any gap count algorithm which employs PHY pinging must compensate for such uncertainty. FIG. 8 depicts a ping subaction issued by the link in Node X and directed to Node Y.

The timing reference points t1 through t7 are identical to those used in the previous gap count derivations. Additionally:

-   -   t₁′ Coincident with the rising SCLK edge in which the PHY first         samples IDLE after a link transmission. t₁′ leads t₁ by         LINK_TO_BUS_DELAY     -   t₇′ Coincident with the rising SCLK edge in which the PHY is         driving the first RECEIVE indication to the link. (The PHY         presumably drove RECEIVE off of the previous clock transition.)         t₇′ lags t₇ by BUS_TO_LINK_DELAY

The ping time measured by the link (in SCLK cycles) is then given by:

$\begin{matrix} \begin{matrix} {{Ping\_ Time}_{meas}^{\lbrack{P_{X}{OP}_{Y}}\rbrack} = {t_{7}^{\prime} - t_{1}^{\prime}}} \\ {= {{{BUS\_ TO}{\_ LINK}{\_ DELAY}_{X,{meas}}} + t_{7} - t_{1} + {{LINK\_ TO}{\_ BUS}{\_ DELAY}_{X,{meas}}}}} \\ {= {{{BUS\_ TO}{\_ LINK}{\_ DELAY}_{X,{meas}}} + {{LINK\_ TO}{\_ BUS}{\_ DELAY}_{X,{meas}}} +}} \\ {t_{0} + {\sum\limits_{n = {X + 1}}^{Y - 1}\begin{pmatrix} {{2 \cdot {cable\_ delay}_{n}} + {PHY\_ DELAY}_{n,{meas}}^{P_{n}^{\prime}->P_{n}} +} \\ {{ARB\_ RESPONSE}{\_ DELAY}_{n,{meas}}^{P_{n}->P_{n}^{\prime}}} \end{pmatrix}} +} \\ {{2 \cdot {cable\_ delay}_{X}} + \frac{packet\_ length}{{packet\_ speed} \cdot {BASERATE}_{Y - 1}} +} \\ {{{DATA\_ END}{\_ TIME}_{{Y - 1},{meas}}^{P_{Y - 1}}} + {RESPONSE\_ TIME}_{Y,{meas}}^{P_{Y}^{\prime}} -} \\ {t_{0} - \frac{packet\_ length}{{packet\_ speed} \cdot {BASERATE}_{X}}} \\ {= {{{BUS\_ TO}{\_ LINK}{\_ DELAY}_{X,{meas}}} + {{LINK\_ TO}{\_ BUS}{\_ DELAY}_{X,{meas}}} +}} \\ {{{Round\_ Trip}{\_ Delay}_{meas}^{\lbrack{P_{X}{OP}_{Y}}\rbrack}} + {PPM\_ delta}^{\lbrack{{Y - 1},X}\rbrack} +} \\ {{{DATA\_ END}{\_ TIME}_{{Y - 1},{meas}}^{P_{Y - 1}}} + {RESPONSE\_ TIME}_{Y,{meas}}^{P_{Y}^{\prime}}} \end{matrix} & (108) \end{matrix}$

Solving for the measured Round_Trip_Delay gives:

$\begin{matrix} {{{Round\_ Trip}{\_ Delay}_{meas}^{\lbrack{P_{X}O\mspace{11mu} P_{Y}}\rbrack}} = {{Ping\_ Time}_{meas}^{\lbrack{P_{X}\mspace{11mu} O\mspace{11mu} P_{Y}}\rbrack} - {{BUS\_ TO}{\_ LINK}{\_ DELAY}_{X,{meas}}} - {{LINK\_ TO}{\_ BUS}{\_ DELAY}_{X,{meas}}} - {PPM\_ delta}^{\lbrack{{Y - 1},X}\rbrack} - {{DATA\_ END}{\_ TIME}_{{Y - 1},{meas}}^{P_{Y - 1}}} - {RESPONSE\_ TIME}_{Y,{meas}}^{P_{Y}^{\prime}}}} & (109) \end{matrix}$

Remembering that RESPONSE_TIME (min or max) absorbs PPM_delta, an upper and lower bound can be defined for Round_Trip_Delay:

$\begin{matrix} {{{Round\_ Trip}{\_ Delay}_{{Ping},\max}^{\lbrack{P_{X}O\mspace{11mu} P_{Y}}\rbrack}} = {{Ping\_ Time}_{meas}^{\lbrack{P_{X}\mspace{11mu} O\mspace{11mu} P_{Y}}\rbrack} - {{BUS\_ TO}{\_ LINK}{\_ DELAY}_{X,\min}} - {{LINK\_ TO}{\_ BUS}{\_ DELAY}_{X,\min}} - {{DATA\_ END}{\_ TIME}_{{Y - 1},\min}^{P_{Y - 1}}} - {RESPONSE\_ TIME}_{Y,\min}^{P_{Y}^{\prime}}}} & (110) \\ {and} & \; \\ {{{Round\_ Trip}{\_ Delay}_{{Ping},\min}^{\lbrack{P_{X}O\mspace{11mu} P_{Y}}\rbrack}} = {{Ping\_ Time}_{meas}^{\lbrack{P_{X}\mspace{11mu} O\mspace{11mu} P_{Y}}\rbrack} - {{BUS\_ TO}{\_ LINK}{\_ DELAY}_{X,\max}} - {{LINK\_ TO}{\_ BUS}{\_ DELAY}_{X,\max}} - {{DATA\_ END}{\_ TIME}_{{Y - 1},\max}^{P_{Y - 1}}} - {RESPONSE\_ TIME}_{Y,\max}^{P_{Y}^{\prime}}}} & (111) \end{matrix}$ such that Round_Trip_Delay_(Ping,min) ^([P) ^(X) ^(OP) ^(Y) ^(])≦Round_Trip_Delay_(meas) ^([P) ^(X) ^(OP) ^(Y) ^(])≦Round_Trip_Delay_(Ping,max) ^([P) ^(X) ^(OP) ^(Y) ^(])  (112)

Using the Round_Trip_Delay properties and the Ping_Time relationships, the maximum Round_Trip_Delay between two given leaf nodes can be bounded for any possible topology.

The simplest and most accurate Round_Trip_Delay determination is afforded when the Bus Manager is one of the leaf nodes in question as shown in FIG. 9.

From (92),

$\begin{matrix} {{{Round\_ Trip}{\_ Delay}_{\max}^{\lbrack{P_{BM}{OP}_{Y}}\rbrack}} \leq {{{Round\_ Trip}{\_ Delay}_{{meas}_{1}}^{\lbrack{P_{BM}{OP}_{Y}}\rbrack}} + {\sum\limits_{n}^{({{BM},Y})}{2 \cdot {Jitter}_{n}}}}} & (113) \end{matrix}$ And from (112),

$\begin{matrix} {{{Round\_ Trip}{\_ Delay}_{\max}^{\lbrack{P_{BM}O\mspace{11mu} P_{Y}}\rbrack}} \leq {{{Round\_ Trip}{\_ Delay}_{{Ping},\max}^{\lbrack{P_{BM}O\mspace{11mu} P_{Y}}\rbrack}} + {\overset{({{BM},Y})}{\sum\limits_{n}}{2 \cdot {Jitter}_{n}}}}} & (114) \end{matrix}$ Likewise, the reverse path is also bounded:

$\begin{matrix} {{{Round\_ Trip}{\_ Delay}_{\max}^{\lbrack{P_{Y}O\mspace{11mu} P_{BM}}\rbrack}} \leq {{{Round\_ Trip}{\_ Delay}_{{Ping},\max}^{\lbrack{P_{BM}O\mspace{11mu} P_{Y}}\rbrack}} + {\overset{({{BM},Y})}{\sum\limits_{n}}{2 \cdot {Jitter}_{n}}}}} & (115) \end{matrix}$

The second topology to consider is when the bus manager is not a leaf but is part of the connecting path between the two leaves as illustrated in, FIG. 10.

Expressing the max delay piecewise,

$\begin{matrix} {{{Round\_ Trip}{\_ Delay}_{\max}^{\lbrack{P_{X}O\mspace{11mu} P_{Y}}\rbrack}} = {{{Round\_ Trip}{\_ Delay}_{\max}^{\lbrack{P_{X}O\mspace{11mu} P_{BM}}\rbrack}} + {{Round\_ Trip}{\_ Delay}_{\max}^{\lbrack{P_{BM}O\mspace{11mu} P_{Y}}\rbrack}} + {PHY\_ DELAY}_{{BM},\max}^{P_{BM}^{\prime}\rightarrow{P_{BM}}} + {{ARB\_ RESPONSE}{\_ DELAY}_{{BM},\max}^{P_{BM}\rightarrow P_{BM}^{\prime}}}}} & (116) \end{matrix}$

Equations (92) and (96) allow:

$\begin{matrix} {{{Round\_ Trip}{\_ Delay}_{\max}^{\lbrack{P_{X}O\mspace{11mu} P_{Y}}\rbrack}} \leq {{{Round\_ Trip}{\_ Delay}_{meas}^{\lbrack{P_{BM}O\mspace{11mu} P_{X}}\rbrack}} + {\sum\limits_{n}^{({{BM},X})}{2 \cdot {Jitter}_{n}}} + {{Round\_ Trip}{\_ Delay}_{meas}^{\lbrack{P_{BM}O\mspace{11mu} P_{Y}}\rbrack}} + {\sum\limits_{n}^{({{BM},Y})}{2 \cdot {Jitter}_{n}}} + {PHY\_ DELAY}_{{BM},\max}^{P_{BM}^{\prime}\rightarrow P_{BM}} + {{ARB\_ RESPONSE}{\_ DELAY}_{{BM},\max}^{P_{BM}\rightarrow P_{BM}^{\prime}}}}} & (117) \end{matrix}$ And from (112),

$\begin{matrix} {{{Round\_ Trip}{\_ Delay}_{\max}^{\lbrack{P_{X}O\mspace{11mu} P_{Y}}\rbrack}} \leq {{{Round\_ Trip}{\_ Delay}_{{Ping},\max}^{\lbrack{P_{BM}O\mspace{11mu} P_{X}}\rbrack}} + {\sum\limits_{n}^{({{BM},X})}{2 \cdot {Jitter}_{n}}} + {{Round\_ Trip}{\_ Delay}_{{Ping},\max}^{\lbrack{P_{BM}O\mspace{11mu} P_{Y}}\rbrack}} + {\sum\limits_{n}^{({{BM},Y})}{2 \cdot {Jitter}_{n}}} + {PHY\_ DELAY}_{{BM},\max}^{P_{BM}^{\prime}\rightarrow P_{BM}} + {{ARB\_ RESPONSE}{\_ DELAY}_{{BM},\max}^{P_{BM}\rightarrow P_{BM}^{\prime}}}}} & (118) \end{matrix}$

Likewise, the reverse path is also bounded:

$\begin{matrix} {{{Round\_ Trip}{\_ Delay}_{\max}^{\lbrack{P_{X}O\mspace{11mu} P_{Y}}\rbrack}} \leq {{{Round\_ Trip}{\_ Delay}_{{Ping},\max}^{\lbrack{P_{BM}O\mspace{11mu} P_{X}}\rbrack}} + {\sum\limits_{n}^{({{BM},X})}{2 \cdot {Jitter}_{n}}} + {{Round\_ Trip}{\_ Delay}_{{Ping},\max}^{\lbrack{P_{BM}O\mspace{11mu} P_{Y}}\rbrack}} + {\sum\limits_{n}^{({{BM},Y})}{2 \cdot {Jitter}_{n}}} + {PHY\_ DELAY}_{{BM},\max}^{P_{BM}^{\prime}\rightarrow P_{BM}} + {{ARB\_ RESPONSE}{\_ DELAY}_{{BM},\max}^{P_{BM}\rightarrow P_{BM}^{\prime}}}}} & (119) \end{matrix}$

The final topology to consider is when the bus manager is not a leaf but is not part of the connecting path between the two leaves as illustrated in FIG. 11.

Expressing the max delay piecewise, Round_Trip_Delay_(max) ^([P) ^(X) ^(OP) ^(Y) ^(])=Round_Trip_Delay_(max) ^([P) ^(X) ^(OP) ^(N) ^(])+Round_Trip_Delay_(max) ^([P) ^(N) ^(OP) ^(Y) ^(])+PHY_Delay_(N,max) ^(P′) ^(N) ^(→P) ^(N) +ARB_RESPONSE_DELAY_(N,max) ^(P) ^(N) ^(→P′) ^(N)   (120)

Equations (107) and (101) allow:

$\begin{matrix} {{{Round\_ Trip}{\_ Delay}_{\max}^{\lbrack{P_{X}O\mspace{11mu} P_{Y}}\rbrack}} \leq {\begin{pmatrix} {{{Round\_ Trip}{\_ Delay}_{{meas}_{1}}^{\lbrack{P_{BM}O\mspace{11mu} P_{Y}}\rbrack}} + {\sum\limits_{n}^{({{BM},X})}{2 \cdot {Jitter}_{n}}} -} \\ {{{Round\_ Trip}{\_ Delay}_{{meas}_{2}}^{\lbrack{P_{BM}O\mspace{11mu} P_{N}}\rbrack}} - {PHY\_ DELAY}_{N,\min}^{P_{N}^{BM}\rightarrow P_{N}^{\prime}} -} \\ {{{ARB\_ RESPONSE}{\_ DELAY}_{N,\min}^{P_{N}^{\prime}\rightarrow{\overset{.}{P}}_{N}^{BM}}} - {2 \cdot {Jitter}_{N}}} \end{pmatrix} + \begin{pmatrix} {{{Round\_ Trip}{\_ Delay}_{{meas}_{1}}^{\lbrack{P_{BM}O\mspace{11mu} P_{Y}}\rbrack}} + {\sum\limits_{n}^{({{BM},Y})}{2 \cdot {Jitter}_{n}}} -} \\ {{{Round\_ Trip}{\_ Delay}_{{meas}_{2}}^{\lbrack{P_{BM}O\mspace{11mu} P_{N}}\rbrack}} - {PHY\_ DELAY}_{N,\min}^{P_{N}^{BM}\rightarrow P_{N}} -} \\ {{{ARB\_ RESPONSE}{\_ DELAY}_{N,\min}^{{\overset{.}{P}}_{N}\rightarrow P_{N}^{BM}}} - {2 \cdot {Jitter}_{N}}} \end{pmatrix} + {PHY\_ DELAY}_{N,\max}^{P_{N}^{\prime}\rightarrow P_{N}} + {{ARB\_ RESPONSE}{\_ DELAY}_{N,\max}^{P_{N}\rightarrow P_{N}^{\prime}}}}} & (121) \end{matrix}$

And from (112),

$\begin{matrix} {{{Round\_ Trip}{\_ Delay}_{\max}^{\lbrack{P_{X}O\mspace{11mu} P_{Y}}\rbrack}} \leq {\begin{pmatrix} {{{Round\_ Trip}{\_ Delay}_{{Ping},\max}^{\lbrack{P_{BM}O\mspace{11mu} P_{X}}\rbrack}} + {\sum\limits_{n}^{({{BM},X})}{2 \cdot {Jitter}_{n}}} +} \\ {{{Round\_ Trip}{\_ Delay}_{{Ping},\max}^{\lbrack{P_{BM}O\mspace{11mu} P_{Y}}\rbrack}} + {\sum\limits_{n}^{({{BM},Y})}{2 \cdot {Jitter}_{n}}} +} \\ {{PHY\_ DELAY}_{N,\max}^{P_{N}^{\prime}\rightarrow P_{N}} + {{ARB\_ RESPONSE}{\_ DELAY}_{N,\max}^{P_{N}\rightarrow P_{N}^{\prime}}}} \end{pmatrix} - \begin{pmatrix} {{{2 \cdot {Round\_ Trip}}{\_ Delay}_{{Ping},\min}^{\lbrack{P_{BM}O\mspace{11mu} P_{N}}\rbrack}} + {4 \cdot {Jitter}_{N}} +} \\ {{PHY\_ DELAY}_{N,\min}^{P_{N}^{BM}\rightarrow P_{N}^{\prime}} +} \\ {{{ARB\_ RESPONSE}{\_ DELAY}_{N,\min}^{P_{N}^{\prime}\rightarrow P_{N}^{BM}}} +} \\ {{PHY\_ DELAY}_{N,\min}^{P_{N}^{BM}\rightarrow P_{N}} +} \\ {{ARB\_ RESPONSE}{\_ DELAY}_{N,\min}^{P_{N}\rightarrow P_{N}^{BM}}} \end{pmatrix}}} & (122) \end{matrix}$ ARB_RESPONSE_DELAY is a difficult parameter to characterize. Proper PHY operation requires that arb signals propagate at least as fast as the data bits, otherwise the arbitration indications could shorten as they are repeated through a network. This fact places a bound on the maximum ARB_RESPONSE_DELAY: ARB_RESPONSE_DELAY between two ports at a particular instant must always be less than or equal to the data repeat delay at the very same instant. Although the distinction is subtle, this is not the same as saying the maximum ARB_RESPONSE_DELAY is PHY_DELAY. (PHY_DELAY only applies to the first bit of a packet and is known to have some jitter from one repeat operation to the next. Consequently, requiring ARB_RESPONSE_DELAY<=PHY_DELAY doesn't force ARB_RESPONSE_DELAY to track the instantaneous PHY_DELAY nor does it allow ARB_RESPONSE_DELAY to track the data repeat time for the last bit of a packet which may actually exceed PHY_DELAY due to PPM drift.) Finally, the table approach to calculating gap_counta and gap_countb rely on ARB_RESPONSE_DELAY always being bounded by the maximum PHY_DELAY when determining the Round_Trip_Delay.

The minimum ARB_RESPONSE_DELAY is only of significance when calculating Data_Arb_Mismatch as required by gap_countc and gap_countd. Ideally, Data_Arb_Mismatch should be a constant regardless of PHY_DELAY so that neither gap countc nor gap countd will begin to dominate the gap count setting as PHY_DELAY increases. Consequently, the minimum ARB_RESPONSE_DELAY should track the instantaneous PHY_DELAY with some offset for margin. Simply specifying the min value as a function of PHY_DELAY is ambiguous, however, since PHY_DELAY can be easily confused with the max DELAY reported in the register map. (For example, with DELAY at 144 ns, it would be easy to assume a min of PHY_DELAY −60 ns would be equivalent to 84 ns. But if the worst case first bit repeat delay was only 100 ns, arb signals repeating with a delay of 40 ns ought to be considered within spec even though the delay is <84 ns.)

Consequently, specifying an upper and a lower bound for ARB_RESPONSE_DELAY is best done in the standard with words rather than values. The minimum and maximum values for ARB_RESPONSE_DELAY include that between all ordered pairs of ports, the PHY shall repeat arbitration line states at least as fast as clocked data, but not more than 60 ns faster than clocked data.

A better approach is to replace ARB_RESPONSE_DELAY with the parameter DELAY_MISMATCH which is defined in the comment column as “Between all ordered pairs of ports, the instantaneous repeat delay for data less the instantaneous repeat delay for arbitration line states.” Then, the minimum would be given as 0 ns and the maximum would be 60 ns.

For a table based calculation of Round_Trip_Delay, either approach above allows the use of PHY_DELAY(max) for ARB_RESPONSE_DELAY. Since Round_Trip_Delay considers the arbitration repeat delay in the direction opposite to the original packet flow, the return arbitration indication of interest is known to arrive at the receive port when the PHY is idle (all caught up with nothing to repeat). At that point, the instantaneous PHY_DELAY is the same as the first data bit repeat delay which is bounded by PHY_DELAY(max). Since ARB_RESPONSE_DELAY, is always bounded by the instantaneous PHY_DELAY, it to is bounded by PHY_DELAY(max) at the point the arbitration indication first arrives.

The minimum bound on PHY_DELAY is used by the bus manager when determining the round_trip_delay between leaf nodes that are not separated by the bus manager. The more precise the minimum bound, the more accurate the pinging calculation can be. Ideally then, the bound may want to scale with increasing PHY_DELAY. Alternatively, the lower bound could be calculated by xamining the Delay field in the register map: if zero, the lower bound is assumed to be the fixed value specified (60 ns currently). If non-zero, the lower bound could then be determined by subtracting the jitter field (converted to ns) from the delay field (converted to ns).

The “Jitter” field was introduced to aid in selection of gap_count via pinging by describing the uncertainty found in any empirical measurement of Round_Trip_Delay. Since Round_Trip_Delay encompasses an “outbound” PHY_DELAY and a “return” ARB_RESPONSE_DELAY, the jitter term should capture uncertainty in both. The needs of pinging can be met with the following description for jitter: Upper bound of the mean average of the worst case data repeat jitter (max/min variance) and the worst case arbitration repeat jitter (max/minvariance), expressed as 2*(jitter+1)/BASE_RATE.

Note that from the discussion on minimum PHY_DELAY, it may be desirable to require that if the delay field is non-zero, then the slowest first data bit repeat delay can be calculated by subtracting the jitter value from the delay value. 

1. A storage apparatus comprising a computer readable medium, the medium comprising a program having a plurality of instructions which, when executed by a computer, enforces a gap count parameter by: setting a first value to be greater than the largest idle period allowable during a first interval; setting a second value to be greater than the largest period allowable for a second interval; requiring that a first idle period observed is repeated with a period not less than the largest idle period allowable during the first interval; and requiring that a second idle period observed is repeated with a period not less than the largest period allowable for the second interval.
 2. The storage apparatus of claim 1, wherein the first interval comprises a subaction.
 3. The storage apparatus of claim 1, wherein the first interval comprises an isochronous interval.
 4. The storage apparatus of claim 1, wherein the second interval comprises a subaction gap.
 5. The storage apparatus of claim 1, wherein the first value comprises a subaction gap timeout.
 6. The storage apparatus of claim 1, wherein the second value comprises an arbitration reset timeout.
 7. An apparatus for enforcing a substantially optimized gap count parameter associated with a data bus, said apparatus comprising: a first module adapted to store a first variable greater than the largest idle period allowable during a first interval; a second module adapted to store a second variable greater than the largest period allowable for a second interval; a third module adapted to calculate a substantially optimal gap count parameter based at least in part upon said first and second variables; and a fourth module adapted to ensure that an idle period observed is not repeated with a period less than at least one of said first and second variables.
 8. The apparatus of claim 7, wherein the data bus comprises a serial bus, and the first interval comprises at least one of a subaction and an isochronous interval.
 9. The apparatus of claim 7, wherein the second interval comprises a subaction gap.
 10. The apparatus of claim 7, wherein the first variable comprises a subaction gap timeout value.
 11. The apparatus of claim 7, wherein the second variable comprises an arbitration reset timeout value.
 12. The apparatus of claim 7, wherein the third module is further adapted to calculate a substantially optimal gap count parameter based at least in part upon a maximum round trip delay between a first PHY associated with a first node and a second PHY associated with a second node.
 13. A method for enforcing a substantially optimized gap count parameter associated with a data bus, said method comprising: determining the largest idle period allowable during a first interval; determining the largest period allowable for a second interval; and deriving a gap count parameter based at least in part by setting a first value to be greater than the largest idle period allowable during the first interval, and based at least in part by setting a second value to be greater than the largest period allowable for the second interval.
 14. The method of claim 13, further comprising: requiring that an idle period observed is not repeated with a period less than at least one of the largest idle period allowable during the first interval, and the largest period allowable for the second interval.
 15. The method of claim 13, wherein said deriving a gap count parameter is also based at least in part by calculating a maximum round trip delay between a first PHY associated with a first node and a second PHY associated with a second node.
 16. An apparatus for calculating and enforcing a substantially optimized gap count parameter, said apparatus comprising: a first module adapted to receive first data, the first data indicating a largest idle period allowable during a first interval; a second module adapted to receive second data, the second data indicating a largest non-idle period allowable for a second interval; and a third module adapted to calculate a gap parameter by a process comprising setting a value such that the value exceeds the largest idle period allowable during the first interval, and further based at least in part on the largest non-idle period allowable for the second interval.
 17. The apparatus of claim 16, wherein the value comprises a subaction gap timeout.
 18. The apparatus of claim 16, wherein the first interval comprises a subaction.
 19. The apparatus of claim 16, wherein the first interval comprises an isochronous interval.
 20. The apparatus of claim 16, wherein the second interval comprises a subaction gap.
 21. An apparatus for calculating and enforcing a substantially optimized gap count parameter, the apparatus comprising: a first module adapted to receive first data, the first data indicating a largest idle period allowable during a first interval; a second module adapted to receive second data, the second data indicating a largest non-idle period allowable for a second interval; and a third module adapted to calculate a gap parameter based at least in part upon the largest idle period allowable during the first interval, and the largest non-idle period allowable for the second interval; a fourth module adapted to ensure that a first idle period observed is repeated with a period not less than the largest idle period allowable during the first interval; and a fifth module adapted to ensure that a second idle period observed is repeated with a period not less than the largest period allowable for the non-idle second interval.
 22. The apparatus of claim 21, wherein the third module is further adapted to calculate the gap parameter by a process comprising setting a value such that the value exceeds the largest period allowable for the non-idle second interval.
 23. The apparatus of claim 22, wherein the value comprises an arbitration reset gap.
 24. A method for enforcing a gap count parameter for use in a serial data bus, said method comprising: receiving first data, the first data indicating the largest idle period allowable during a first interval; receiving second data, the second data indicating the largest period allowable for a second interval; deriving at least a first value and a second value from the first and second data; and determining a gap count parameter based at least in part by setting a value greater than or equal to at least one of the first or second values; wherein the first interval comprises at least one of a subaction and/or an isochronous interval.
 25. The method of claim 24, wherein the second interval comprises a subaction gap.
 26. The method of claim 24, further comprising: requiring that a first idle period observed is repeated with a period not less than the largest idle period allowable during the first interval.
 27. The method of claim 24, further comprising: requiring that a second idle period observed is repeated with a period not less than the largest period allowable for the second interval. 